Lecture 10 The Processor

Lecture 10 The Processor - Chapter 4 The Processor 4.9...

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Chapter 4 The Processor
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Chapter 4 — The Processor — 2 Exceptions and Interrupts ± “Unexpected” events requiring change in flow of control ± Different ISAs use the terms differently ± Exception ± Arises within the CPU ± e.g., undefined opcode, overflow, syscall, … ± Interrupt ± From an external I/O controller ± Dealing with them without sacrificing performance is hard §4.9 Exceptions
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Chapter 4 — The Processor — 3 Handling Exceptions ± In MIPS, exceptions managed by a System Control Coprocessor (CP0) ± Save PC of offending (or interrupted) instruction ± In MIPS: Exception Program Counter (EPC) ± Save indication of the problem ± In MIPS: Cause register ± We’ll assume 1-bit ± 0 for undefined opcode, 1 for overflow ± Jump to handler at 8000 00180
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Chapter 4 — The Processor — 4 An Alternate Mechanism ± Vectored Interrupts ± Handler address determined by the cause ± Example: ± Undefined opcode: C000 0000 ± Overflow: C000 0020 ± …: C000 0040 ± Instructions either ± Deal with the interrupt, or ± Jump to real handler
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Chapter 4 — The Processor — 5 Handler Actions ± Read cause, and transfer to relevant handler ± Determine action required ± If restartable ± Take corrective action ± use EPC to return to program ± Otherwise ± Terminate program ± Report error using EPC, cause, …
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Chapter 4 — The Processor — 6 Exceptions in a Pipeline ± Another form of control hazard ± Consider overflow on add in EX stage add $1, $2, $1 ± Prevent $1 from being clobbered ± Complete previous instructions ± Flush add and subsequent instructions ± Set Cause and EPC register values ± Transfer control to handler ± Similar to mispredicted branch ± Use much of the same hardware
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Chapter 4 — The Processor — 7 Pipeline with Exceptions
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Chapter 4 — The Processor — 8 Exception Properties ± Restartable exceptions ± Pipeline can flush the instruction ± Handler executes, then returns to the instruction ± Refetched and executed from scratch ± PC saved in EPC register ± Identifies causing instruction ± Actually PC + 4 is saved ± Handler must adjust
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Chapter 4 — The Processor — 9 Exception Example ± Exception on add in 40 sub $11, $2, $4 44 and $12, $2, $5 48 or $13, $2, $6 4C add $1, $2, $1 50 slt $15, $6, $7 54 lw $16, 50($7) ± Handler 80000180 sw $25, 1000($0) 80000184 sw $26, 1004($0)
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Chapter 4 — The Processor — 10 Exception Example
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Chapter 4 — The Processor — 11 Exception Example
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Chapter 4 — The Processor — 12 Multiple Exceptions ± Pipelining overlaps multiple instructions ± Could have multiple exceptions at once ± Simple approach: deal with exception from earliest instruction ± Flush subsequent instructions ± “Precise” exceptions ± In complex pipelines ± Multiple instructions issued per cycle ± Out-of-order completion ± Maintaining precise exceptions is difficult!
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Chapter 4 — The Processor — 13 Imprecise Exceptions ± Just stop pipeline and save state ± Including exception cause(s)
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Lecture 10 The Processor - Chapter 4 The Processor 4.9...

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