Practice Final

Practice Final - UNIVERSITY OF CALIFORNIA, LOS ANGELES `...

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UNIVERSITY OF CALIFORNIA, LOS ANGELES UCLA CS M151B / EE M116C Final Exam Before you start, make sure you have all 13 pages attached to this cover sheet. All work and answers should be written directly on these pages, use the backs of pages if needed. This is an open book, open notes final – but you cannot share books, notes, or calculators. NAME: ________________________________________________________________ ID: ____________________________________________________________________ Problem 1 (10 points): ___________ Problem 2 (10 points): ___________ Problem 3 (10 points): ___________ Problem 4 (10 points): ___________ Problem 5 (20 points): ___________ Problem 6 (10 points): ___________ Problem 7 (30 points): ___________ Total: ________________ (out of 100 points) `` BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ
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1 1. I Amdahl-ighted with Tradeoffs (10 points): Given the following problems, suggest one solution and give one drawback of the solution. Be brief, but specific. EXAMPLE Problem: long memory latencies Solution: Caches Drawback: when the cache misses, the latency becomes worse due to the cache access latency We would not accept solutions like : “do not use memory”, “use a slower CPU”, “cache is hard to spell”, etc Problem: too many capacity misses in the data cache Solution: drawback: Problem: too many control hazards Solution: drawback: Problem: our carry lookahead adder is too slow Solution: drawback: Problem: we want to be able to use a larger immediate field in the MIPS ISA Solution: drawback: Problem: the execution time of our CPU with a single-cycle datapath is too high Solution: drawback:
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2 2. Hazard a Guess? (10 points): Assume you are using the 5-stage pipelined MIPS processor, with a three-cycle branch penalty. Further assume that we always use predict not taken. Consider the following instruction sequence, where the bne is taken once, and then not taken once (so 7 instructions will be executed total): Loop : lw $t0, 512($t0) lw $t1, 64($t0) bne $s0, $t1, Loop sw $s1, 128($t0) Assuming that the pipeline is empty before the first instruction: a. Suppose we do not have any data forwarding hardware – we stall on data hazards. The register file is still written in the first half of a cycle and read in the second half of a cycle, so there is no hazard from WB to ID. Calculate the number of cycles that this sequence of instructions would take: __________________
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3 b. How many cycles would this sequence of instructions take with data forwarding hardware: _____________________
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4 3. More $ More Problems (10 points): Find the data cache hit or miss stats for a given set of addresses. The data cache is a 1KB, direct mapped cache with 64-byte blocks.
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Practice Final - UNIVERSITY OF CALIFORNIA, LOS ANGELES `...

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