Feasibility Study on the Use of the UP3 Board as a Digital Pattern Generator

Feasibility Study on the Use of the UP3 Board as a Digital Pattern Generator

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Feasibility Study on the Use of the UP3 Board as a Digital Pattern Generator Timothy Gurtler ECE 2031 tgurtler3@gatech.edu Executive Summary: Digital pattern generators are instruments that can produce varying signals that a user can define. This document studies the feasibility of using a UP3 board as a digital pattern generator. The UP3 board contains an FPGA chip that can be programmed to simulate digital circuit designs, such as logic gates, flip flops, and digital patterns. Using the J1 output on the UP3 board, the user is able to simulate the design of the digital pattern generator programmed on the FPGA chip. The user can then control this simulation through an input with a keyboard. This design proves to be efficient and effective in the goal of using the UP3 as a digital pattern generator. 1
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Introduction: This report addresses the feasibility and constraints of using the UP3 board as a digital pattern generator. Some of the constraints include being able to use the UP3-1C6 board as well as the UP3-1C12 board while not requiring any additional hardware beyond what is needed to program and utilize a UP3 board, identifying the best output(s), and the achievability of implementation. In the following pages, this report will look at the benefits and/or problems associated with using the UP3 board as a digital pattern generator. The purpose of this report is to tackle the feasibility this design. Background:
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Feasibility Study on the Use of the UP3 Board as a Digital Pattern Generator

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