Preport-comments - Engineering a Module-Based Digital Pattern Generator on the UP3 Education Board Ben Blount Timothy Gurtler Julienne Kung Kevin

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Engineering a Module-Based Digital Pattern Generator on the UP3 Education Board Ben Blount Timothy Gurtler Julienne Kung Kevin Morgan ECE 2031 Section L07 8 December 2008
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Executive Summary 1
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Introduction Digital hardware requires careful testing to ensure correct operation. As it is inefficient to do this manually, a digital pattern generator (DPG) is often employed to automate the process. The objective of this project was to develop a DPG that operates on a UP3 Education Board that would be potentially suitable for industrial or commercial applications. The DPG had to conform to the following constraints: Works equally well on a UP3-C6 or UP3-C12 board Requires only the following hardware: o A power supply o A PC for programming, downloading, and controlling the DPG o An on-board LCD or external VGA display o PS/2 Keyboard or Mouse o Serial or USB cables Provide all outputs on J1, J2, or J3 The proposed DPG (see Appendix A for proposal) met these constraints by employing a custom, module-based architecture employing several state machines operating in parallel as opposed to a readily available computer like SCOMP. This design allowed easy integration of pattern modules, a user interface employing a PS/2 keyboard and VGA display, and a PC based set of tools for designing and transferring user-defined patterns. The final implementation conformed to most of these proposed features, but lacked the ability to transfer user-defined patterns in real time via the RS-232 serial protocol. Architecture changes were made to reduce clock skew in the device by removing clock multiplexers from the design at the cost of requiring more complex communication between the different modules in the design. Testing showed that the design sufficiently met its proposed design goals, but also has room for future improvement. As is, the device is suitable for its target application in providing test stimulus for ASICs and programmable logic controllers (PLCs) used in devices from gaming systems to factory 2
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automation systems. Further application in control applications, such as motor controllers and digital control systems, became apparent as the device was developed. While the device requires more thorough debugging to become commercially viable, it currently is a good base to pursue further development. General Methodology The final architecture is shown in Figure 1. The project was approached from a modular aspect intended to increase device speed and flexibility as well as ease project management. The architecture consists of three primary modules: control hardware, pattern modules, and user interface. The entire FPGA side of the DPG was implemented in VHDL. A separate PC tool-chain for the DPG was implemented in Perl to allow user-defined patterns. Source files are available in Appendix F. The modular design allowed each piece of hardware to be tested separately. This resulted in straightforward integration of each module and significantly simplified debugging by isolating problems to individual modules. Project Management
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This note was uploaded on 04/19/2010 for the course ECE 2040 taught by Professor Yili during the Spring '08 term at Georgia Institute of Technology.

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Preport-comments - Engineering a Module-Based Digital Pattern Generator on the UP3 Education Board Ben Blount Timothy Gurtler Julienne Kung Kevin

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