1.VerilogCodingEfficiency - VERILOG CODING STYLES FOR...

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VERILOG CODING STYLES FOR IMPROVED SIMULATION EFFICIENCY Clifford E. Cummings [email protected] / www.sunburst-design.com Sunburst Design, Inc. 14314 SW Allen Blvd. PMB 501 Beaverton, OR 97005 INTERNATIONAL CADENCE USER GROUP CONFERENCE OCTOBER 5-9, 1997 SAN DIEGO, CALIFORNIA
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International Cadence Users Group 1997 Verilog Coding Styles For Improved Rev 1.1 Simulation Efficiency 2 Verilog Coding Styles for Improved Simulation Efficiency Clifford E. Cummings Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97007 Phone: 503-641-8446 Email: [email protected] Abstract This paper details different coding styles and their impact on Verilog-XL simulation efficiency. 1. Introduction What are some of the more optimal ways to code Verilog models and testbenches to shorten simulation times? This paper is a collection of interesting coding style comparisons that have been run on Verilog-XL. 2. Verilog Efficiency Testing The intent of this paper is to help identify which Verilog coding styles are more efficient than others; thereby, increasing design and simulation efficiency. All of the Verilog benchmarks in this paper are intended to show the efficiency of how specific coding styles run on the same simulator. This paper is not intended to be a benchmark comparison between different simulators. All of the benchmarks were run on a Sparc 5, running Solaris 2.5, with 32MB of memory and 500MB of swap space. Verilog-XL, version 2.21, compiled with Undertow version 5.3.3, was used for these benchmarks. Note: over time, measured efficiency will likely change as newer versions of the same simulator are introduced and as simulators become more efficient. 3. Case Statements Vs. Large If/Else-If Structures Question: Is there a simulation efficiency difference in coding large case statements as equivalent if/else-if statements? The testcase for this benchmark is a synthesizable 8-to-1 multiplexer written as both a case statement and as a large if/else-if construct. Figure 1 shows the code for the case-statement multiplexer, Figure 2 shows the code for the equivalent if/else-if-statement multiplexer. 3.1 Case Vs. If Efficiency Summary The results in Table 1 show that, using Verilog-XL, this 8-item case structure took about the same amount of memory to implement as the if/else-if structure but the case statement was about 6% faster. module CaseMux8 (y, i, sel); output y; input [7:0] i; input [2:0] sel; reg y; wire [7:0] i; wire [2:0] sel; always @(i or sel) case (sel) 3'd0: y = i[0]; 3'd1: y = i[1]; 3'd2: y = i[2]; 3'd3: y = i[3]; 3'd4: y = i[4]; 3'd5: y = i[5]; 3'd6: y = i[6]; 3'd7: y = i[7]; endcase endmodule Figure 1 module IfMux8 (y, i, sel); output y; input [7:0] i; input [2:0] sel; reg y; wire [7:0] i; wire [2:0] sel; always @(i or sel) if (sel == 3'd0) y = i[0]; else if (sel == 3'd1) y = i[1]; else if (sel == 3'd2) y = i[2]; else if (sel == 3'd3) y = i[3]; else if (sel == 3'd4) y = i[4]; else if (sel == 3'd5) y = i[5]; else if (sel == 3'd6) y = i[6]; else if (sel == 3'd7) y = i[7]; endmodule Figure 2
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This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

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1.VerilogCodingEfficiency - VERILOG CODING STYLES FOR...

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