2.FSMFundamentals - The Fundamentals of Efficient...

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The Fundamentals of Efficient Synthesizable Finite State Machine Design using NC-Verilog and BuildGates Clifford E. Cummings Sunburst Design, Inc. 503-641-8446 cliffc@sunburst-design.com INTERNATIONAL CADENCE USERGROUP CONFERENCE September 16-18, 2002 San Jose, California ICU-2002 San Jose, CA Voted Best Paper 2 nd Place
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International Cadence Users Group 2002 Fundamentals of Efficient Synthesizable FSM Rev 1.2 Design using NC-Verilog and BuildGates 2 Abstract This paper details proven RTL coding styles for efficient and synthesizable Finite State Machine (FSM) design using IEEE-compliant Verilog simulators. Important techniques related to one and two always block styles to code FSMs with combinational outputs are given to show why using a two always block style is preferred. An efficient Verilog-unique onehot FSM coding style is also shown. Reasons and techniques for registering FSM outputs are also detailed. Myths surrounding erroneous state encodings, full-case and parallel-case usage are also discussed. Compliance and enhancements related to the IEEE 1364-2001 Verilog Standard, the proposed IEEE 1364.1 Verilog Synthesis Interoperability Standard and the proposed Accellera SystemVerilog Standard are also discussed. 1. Introduction FSM is an abbreviation for Finite State Machine . There are many ways to code FSMs including many very poor ways to code FSMs. This paper will examine some of the most commonly used FSM coding styles, their advantages and disadvantages, and offer guidelines for doing efficient coding, simulation and synthesis of FSM designs. This paper will also detail Accellera SystemVerilog enhancements that will facilitate and enhance future Verilog FSM designs. In this paper, multiple references are made to combinational always blocks and sequential always blocks. Combinational always blocks are always blocks that are used to code combinational logic functionality and are strictly coded using blocking assignments (see Cummings[4]). A combinational always block has a combinational sensitivity list, a sensitivity list without "posedge" or "negedge" Verilog keywords. Sequential always blocks are always blocks that are used to code clocked or sequential logic and are always coded using nonblocking assignments (see Cummings[4]). A sequential always block has an edge-based sensitivy list. 2. Mealy and Moore FSMs A common classification used to describe the type of an FSM is Mealy and Moore state machines[9][10]. Figure 1 - Finite State Machine (FSM) block diagram
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International Cadence Users Group 2002 Fundamentals of Efficient Synthesizable FSM Rev 1.2 Design using NC-Verilog and BuildGates 3 A Moore FSM is a state machine where the outputs are only a function of the present state. A Mealy FSM is a state machine where one or more of the outputs is a function of the present state and one or more of the inputs. A block diagram for Moore and Mealy FSMs is shown Figure 1. 3. Binary Encoded or Onehot Encoded?
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This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

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2.FSMFundamentals - The Fundamentals of Efficient...

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