3.FSMcodingforsysthesis - State Machine Coding Styles for...

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State Machine Coding Styles for Synthesis Clifford E. Cummings Sunburst Design, Inc. ABSTRACT This paper details efficient Verilog coding styles to infer synthesizable state machines. HDL considerations such as advantages and disadvantages of one-always block FSMs Vs. two-always block FSMs are described.
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SNUG 1998 State Machine Coding Styles for Synthesis Rev 1.1 2 Introduction Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is a great paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper also offers in-depth background concerning the origin of specific state machine types. This paper, "State Machine Coding Styles for Synthesis," details additional insights into state machine design including coding style approaches and a few additional tricks. State Machine Classification There are two types of state machines as classified by the types of outputs generated from each. The first is the Moore State Machine where the outputs are only a function of the present state, the second is the Mealy State Machine where one or more of the outputs are a function of the present state and one or more of the inputs. Figure 1 - FSM Block Diagram In addition to classifying state machines by their respective output-generation type, state machines are also often classified by the state encoding employed by each state machine. Some of the more common state encoding styles include [1] [2] [3]: highly-encoded binary (or binary- sequential), gray-code, Johnson, one-hot, almost one-hot and one-hot with zero-idle (note: in the absence of a known official designation for the last encoding-style listed, the author selected the "one-hot with zero-idle" title. A more generally accepted name may exist). Using the Moore FSM state diagram shown in Figure 2, this paper will detail synthesizable Verilog coding styles for highly-encoded binary, one-hot and one-hot with zero-idle state machines. This paper also details usage of the Synopsys FSM Tool to generate binary, gray and one-hot state machines. Coded examples of the three coding styles for the state machine in Figure Present State FF’s Next State Logic Output Logic next state clock inputs outputs combinational logic combinational logic sequential logic state (Mealy State Machine Only)
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SNUG 1998 State Machine Coding Styles for Synthesis Rev 1.1 3 2, plus an example with the correct Synopsys FSM Tool comments, have been included at the end of this paper. Figure 2 - Benchmark 1 (bm1) State Diagram FSM Verilog Modules Guideline: make each state machine a separate Verilog module. Keeping each state machine separate from other synthesized logic simplifies the tasks of state machine definition, modification and debug. There are also a number of EDA tools that assist in the design and documentation of FSMs, but in general they only work well if the FSM is not mingled with other logic-code.
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This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

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3.FSMcodingforsysthesis - State Machine Coding Styles for...

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