5.MultiAsyncClk - Expert Verilog, SystemVerilog &...

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Expert Verilog, SystemVerilog & Synthesis Training Synthesis and Scripting Techniques for Designing Multi- Asynchronous Clock Designs Clifford E. Cummings, Sunburst Design, Inc. cliffc@sunburst-design.com ABSTRACT Designing a pure, one-clock synchronous design is a luxury that few ASIC designers will ever know. Most of the ASICs that are ever designed are driven by multiple asynchronous clocks and require special data, control-signal and verification handling to insure the timely completion of a robust working design. SNUG-2001 San Jose, CA Voted Best Paper 3rd Place
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SNUG San Jose 2001 Synthesis and Scripting Techniques for Rev 1.2 Designing Multi-Asynchronous Clock Designs 2 1.0 Introduction Most college courses teach engineering students prescribed techniques for designing completely synchronous (single clock) logic. In the real ASIC design world, there are very few single clock designs. This paper will detail some of the hardware design, timing analysis, synthesis and simulation methodologies to address multi-clock designs. This paper is not intended to provide exhaustive coverage of this topic, but is presented to share techniques learned from experience. 2.0 Metastability Quoting from Dally and Poulton's book[6] concerning metastability: "When sampling a changing data signal with a clock . .. the order of the events determines the outcome. The smaller the time difference between the events, the longer it takes to determine which came first. When two events occur very close together, the decision process can take longer than the time allotted, and a synchronization failure occurs." Data changing bclk samples adat while it is changing aclk bclk dat adat bdat1 adat bdat1 aclk bclk Clocked signal is initially metastable . .. ... and might still be metastable at the next rising edge of bclk aclk is asynchronous to bclk Only one synchronizing flip-flop Figure 1 - Asynchronous clocks and synchronization failure Figure 1 shows a synchronization failure that occurs when a signal generated in one clock domain is sampled too close to the rising edge of a clock signal from another clock domain. Synchronization failure is caused by an output going metastable and not converging to a legal stable state by the time the output must be sampled again. Figure 2 shows that a metastable output can cause illegal signal values to be propagated throughout the rest of the design.
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SNUG San Jose 2001 Synthesis and Scripting Techniques for Rev 1.2 Designing Multi-Asynchronous Clock Designs 3 aclk bclk dat adat bdat1 adat bdat1 aclk bclk "1" "0" ?? ?? ?? ?? adat changing Sampling clock Clocked signal is initially metastable and is still meta- stable on the next active clock edge Other logic output values are indeterminate invalid data propagated throughout the design Figure 2 - Metastable bdat1 output propagating invalid data throughout the design Every flip-flop that is used in any design has a specified setup and hold time, or the time in which the data input is not legally permitted to change before and after a rising clock edge. This time window is specified as a design
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This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

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5.MultiAsyncClk - Expert Verilog, SystemVerilog &...

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