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6.FIFO1 - Expert Verilog SystemVerilog Synthesis Training...

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Expert Verilog, SystemVerilog & Synthesis Training Simulation and Synthesis Techniques for Asynchronous FIFO Design Clifford E. Cummings, Sunburst Design, Inc. [email protected] ABSTRACT FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included. Post-SNUG Editorial Comment A second FIFO paper by the same author was voted “Best Paper - 1 st Place” by SNUG attendees, is listed as reference [3] and is also available for download.
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