7.FIFO2 - Expert Verilog, SystemVerilog & Synthesis...

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Expert Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons Clifford E. Cummings Peter Alfke Sunburst Design, Inc. Xilinx, Inc. ABSTRACT An interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFO comparison method requires additional techniques to correctly synthesize and analyze the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built- in binary ripple carry logic. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #2) is included. This FIFO design paper builds on information already presented in another FIFO design paper where the FIFO pointers are synchronized into the opposite clock domain before running "FIFO full" or "FIFO empty" tests. The reader may benefit from first reviewing the FIFO Style #1 method before proceeding to this FIFO Style #2 method. Post-SNUG Editorial Comment (by Cliff Cummings) Although this paper was voted “Best Paper - 1 st Place” by SNUG attendees, this paper builds off of a second FIFO paper listed as reference [1]. The first FIFO paper laid the foundation for some of the content of this paper; therefore, it is highly recommended that readers download and read the FIFO1 paper[1] to acquire background information already assumed to be known by the reader of this paper. SNUG-2002 San Jose, CA Voted Best Paper 1 st Place
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SNUG San Jose 2002 Simulation and Synthesis Techniques for Asynchronous Rev 1.2 FIFO Design with Asynchronous Pointer Comparisons 2 1.0 Introduction An asynchronous FIFO refers to a FIFO design where data values are written sequentially into a FIFO buffer using one clock domain, and the data values are sequentially read from the same FIFO buffer using another clock domain, where the two clock domains are asynchronous to each other. One common technique for designing an asynchronous FIFO is to use Gray[4] code pointers that are synchronized into the opposite clock domain before generating synchronous FIFO full or empty status signals[1]. An interesting and different approach to FIFO full and empty generation is to do an asynchronous comparison of the pointers and then asynchronously set the full or empty status bits[6]. This paper discusses the FIFO design style with asynchronous pointer comparison and asynchronous full and empty generation. Important details relating to this style of asynchronous FIFO design are included. The FIFO style implemented in this paper uses efficient Gray code counters, whose implementation is described in the next section. 2.0
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7.FIFO2 - Expert Verilog, SystemVerilog & Synthesis...

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