9.NBAwithdelays - Verilog Nonblocking Assignments With...

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Verilog Nonblocking Assignments With Delays, Clifford E. Cummings Sunburst Design, Inc. cliffc@sunburst-design.com ABSTRACT There is a common misconception that coding sequential logic with nonblocking assignments does not simulate correctly unless a #1 delay is added to the right hand side of the nonblocking assignment operator. This is not true. This paper will explain how delays and nonblocking assignments impact the Verilog event queue. This paper will also detail both good and bad reasons for adding delays to nonblocking assignments and include guidelines for good RTL coding styles that permit mixed RTL and gate-level simulation. SNUG-2002 Boston, MA Voted Best Paper 2 nd Place
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SNUG Boston 2002 Verilog Nonblocking Assignments Rev 1.4 2 1.0 Introduction In his book Writing Testbenches[7], Functional Verification of HDL Models, Janick Bergeron claims that VHDL and Verilog both have the same area under the learning curve[8]. Due to the misinformation that has been spread through numerous Verilog books and training courses, I am afraid Bergeron may be right. When Verilog is taught correctly, I believe the area under the Verilog learning curve is much smaller and Verilog simulations run much faster than comparable VHDL simulations. This paper details functionality and important guidelines related to nonblocking assignments and nonblocking assignments with delays. Before discussing nonblocking assignment functionality and recommendations, a quick review of the definition of nonblocking assignments is in order: A nonblocking assignment is a Verilog procedural assignment that uses the " <= " operator inside of a procedural block. It is illegal to use a nonblocking assignment in a continuous assignment statement or in a net declaration. A nonblocking assignment can be viewed as a 2-step assignment. At the beginning of a simulation time step, the right-hand-side (RHS) of the nonblocking assignment is (1) evaluated and at the end of the nonblocking assignment the left-hand-side (LHS) variable is (2) updated. A nonblocking assignment does not "block" other assignments from being executed between the evaluation and update steps of a nonblocking assignment; hence, the name "nonblocking." Despite complaints from commercial document spell-checking software, nonblocking is spelled without a hyphen, as noted in both IEEE Verilog Standards[4][5] and the pending IEEE Verilog Synthesis Standard[6].
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SNUG Boston 2002 Verilog Nonblocking Assignments Rev 1.4 3 2.0 The Verilog event queue The Verilog event queue described in this paper is an algorithmic description. The exact implementation is not defined in the Verilog Standard but the outcome must duplicate the functionality of the description. Section 5.4 of both IEEE Verilog Standards documents, IEEE Std 1364-1995[4] and IEEE Std
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9.NBAwithdelays - Verilog Nonblocking Assignments With...

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