10.BehavioralDelays_Rev1_1 - Correct Methods For Adding...

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HDLCON 1999 1 Correct Methods For Adding Delays Rev 1.1 To Verilog Behavioral Models Correct Methods For Adding Delays To Verilog Behavioral Models Clifford E. Cummings Sunburst Design, Inc. 15870 SW Breccia Drive Beaverton, OR 97007 [email protected] Abstract Design engineers frequently build Verilog models with behavioral delays. Most hardware description languages permit a wide variety of delay coding styles but very few of the permitted coding styles actually model realistic hardware delays. Some of the most common delay modeling styles are very poor representations of real hardware. This paper examines commonly used delay modeling styles and indicates which styles behave like real hardware, and which do not. 1.0 Introduction One of the most common behavioral Verilog coding styles used to model combinational logic is to place delays to the left of blocking procedural assignments inside of an always block. This coding style is flawed as it can either easily produce the wrong output value or can propagate inputs to an output in less time than permitted by the model specifications. This paper details delay-modeling styles using continuous assignments with delays, and procedural assignments using blocking and nonblocking assignments with delays on either side of the assignment operator. To help understand delay modeling, the next section also includes a short description on inertial and transport delays, and Verilog command line switches that are commonly used to simulate a model that is neither a fully inertial-delay model nor a fully transport-delay model. 2.0 Inertial and transport delay modeling Inertial delay models only propagate signals to an output after the input signals have remained unchanged (been stable) for a time period equal to or greater than the propagation delay of the model. If the time between two input changes is shorter than a procedural assignment delay, a continuous assignment delay, or gate delay, a previously scheduled but unrealized output event is replaced with a newly scheduled output event. Transport delay models propagate all signals to an output after any input signals change. Scheduled output value changes are queued for transport delay models. delay models propagate all signals that are greater than the error setting, propagate unknown settings, and do not propagate signals that fall below the reject setting. For most Verilog simulators, reject and error settings are specified as a percentage of propagation delay in multiples of 10%. Pure inertial delay example using reject/error switches. Add the Verilog command line options: +pulse_r/100 +pulse_e/100 reject all pulses less than 100% of propagation delay. Pure
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This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

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10.BehavioralDelays_Rev1_1 - Correct Methods For Adding...

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