21_09_061 - Memory design and bus interface LogicCircuits...

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Memory design and bus interface
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Synchronization in Digital Logic Circuits Digital Abstraction depends on all signals in a system having a valid  logic state Therefore, Digital Abstraction depends on reliable synchronization of  external events Inputs from the Real World are usually asynchronous to our system  clock
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Metastability When asynchronous events enter our synchronous system, they can  cause bistables to go into metastable states Every real life bistable (such as a D-latch) has a metastable state
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Metastability Once a FF goes metastable (due to a setup time violation, say) we  can’t say when it will assume a valid logic level or what level it might  eventually assume The only thing we know is that the probability of a FF coming out of a  metastable state increases exponentially with time
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Mean time between failures For a FF we can compute its MTBF, which is a figure of merit related to  metastability.
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Synchronizer requirements Synchronizers must be designed to reduce the chances system failure  due to metastability Synchronizer requirements Reliable [high MTBF] Low latency [works as quickly as possible] Low power/area impact
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Single signal synchronizer Traditional synchronizer SIG is asynchronous, and META might go metastable from time to  time However, as long as META resolves before the next clock period  SIG1 should have valid logic levels  Place FFs close together to allow maximum time for META to  reslove
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Single synchronizer analysis MTBF of this system is roughly:  Can increase MTBF by adding more series stages
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Synchronization pitfall Never synchronize the same signal in multiple places! Inconsistency  will result!
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BUS synchronization Obvious approach is to use single signal synchronizers on each bit Wrong
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Handshaking is the answer Sender outputs data and THEN asserts REQ Receiver latches data and THEN asserts ACK Sender deasserts REQ, will not reassert it until ACK deasserts Receiver sees REQ deasserted, deasserts ACK when ready to continue
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Alternate handshaking rules 2-phase (or edge based) handshaking is also suitable Sender outputs data and THEN changes state of REQ, will not  change state of REQ again until after ACK changes state. Receiver latches data. Once receiver is ready for more it changes 
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This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

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21_09_061 - Memory design and bus interface LogicCircuits...

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