Clock_Dividers_Made_Easy - Clock Dividers Made Easy Mohit...

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SNUG Boston,2002 Clock Dividers Made Easy Clock Dividers Made Easy Mohit Arora Design Flow and Reuse (CR&D) ST Microelectronics Ltd Plot No. 2 & 3, Sector 16A Noida-201301, India ( www.st.com ) ABSTRACT Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. This paper talks about implementation of unusual clock dividers. The paper starts up with simple dividers where the clock is divided by an odd number (Divide by 3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper also covers Verilog code implementation for a non-integer divider.
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