Clock_Dividers_Made_Easy - Clock Dividers Made Easy Mohit...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
SNUG Boston,2002 Clock Dividers Made Easy Clock Dividers Made Easy Mohit Arora Design Flow and Reuse (CR&D) ST Microelectronics Ltd Plot No. 2 & 3, Sector 16A Noida-201301, India ( www.st.com ) ABSTRACT Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. This paper talks about implementation of unusual clock dividers. The paper starts up with simple dividers where the clock is divided by an odd number (Divide by 3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper also covers Verilog code implementation for a non-integer divider.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ST Microelectronics Ltd. ______________________________________________________________________________ SNUG Boston,2002 Page 2 Clock Dividers Made Easy INDEX 1. Introduction. ............................................................................................................................... 4 2. Simple clock divider where the input clock is divided by an odd integer . ............................... 4 3. Odd integer division with 50% duty cycle. ................................................................................. 4 4. Non-integer division (duty cycle not 50%). ................................................................................ 6 4.1 Divide by 1.5 with duty cycle not exactly 50%. .......................................................................... 6 4.2 Divide by 4.5 with duty cycle not exactly 50% (counter implementation). .................................... 7 4.2.1 Verilog code for Divide by 4.5 . .......................................................................................... 8 5 Alternative approach for divide by-N . ......................................................................................... 9 5.1 Divide by 1.5 (LUT implementation). ........................................................................................ 9 5.2 Divide by 2.5 (LUT Implementation). ...................................................................................... 11 5.3 Divide by 3 with 50% duty cycle output. .................................................................................. 14 5.4 Divide by 5 with 50% duty cycle output. .................................................................................. 16 6. Conclusions. .............................................................................................................................. 18 7. Acknowledgements. .................................................................................................................. 18 8. References. ................................................................................................................................ 18 9. Author & Contact information. ................................................................................................. 19
Background image of page 2
ST Microelectronics Ltd. ______________________________________________________________________________ SNUG Boston,2002 Page 3 Clock Dividers Made Easy List of Figures Figure 1: Divide by 7 using a Moore Machine . .............................................................................. 4 Figure 2: Timing diagram for Divide by 3 (N=2) with 50% duty cycle output. ............................. 5 Figure 3: Divide by 3 using T flip-flop with 50 % duty cycle output. ............................................ 6 Figure 4: Divide by 1.5 using T flip-flop(Duty cycle not 50%) . .................................................... 6 Figure 5: Timing diagram for Divide by 1.5 using T flip-flop (Duty Cycle not 50%). .................. 7 Figure 6:Timing diagram for counter implementation of Divide by 4.5 (duty cycle not 50%). ..... 8 Figure 7: Divide by 3 (duty cycle not 50%). ................................................................................... 9 Figure 8:Timing diagram for Divide by 3 (duty cycle not 50%) . ................................................... 9 Figure 9: LUT Implementation for Divide by 1.5 (duty cycle output not 50%). .......................... 10 Figure 10: Timing diagram for Divide by 1.5 (LUT implementation) . ........................................ 10 Figure 11: Timing diagram for Divide by 1.5 where input B is delayed with respect to CLK. ....11 Figure 12: Divide by 5 (Duty cycle not 50%). .............................................................................. 12 Figure 13: Timing diagram for Divide by 5 (duty cycle not 50%) . .............................................. 12 Figure 14: LUT Implementation for Divide by 2.5 (duty cycle output not 50%). ........................ 12 Figure 15: Timing diagram for Divide by 2.5 (LUT implementation) . ........................................ 13 Figure 16: LUT Implementation for Divide by 3 (50% duty cycle output). ................................. 15 Figure 17: Timing diagram for Divide by 3 (LUT implementation) . ........................................... 15 Figure 18: LUT Implementation for Divide by 5 (50% duty cycle output). ................................. 17 Figure 19: Timing diagram for Divide by 5 (LUT implementation) . ........................................... 17 List of Tables Table 1: LUT and the Output table for Divide by 1.5 circuit. ....................................................... 11 Table 2: LUT and the Output table for Divide by 2.5 circuit. ....................................................... 14 Table 3: LUT table output for Divide by 3 circuit. ....................................................................... 16 Table 4: LUT output table for Divide by 5 circuit. ....................................................................... 18
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ST Microelectronics Ltd.
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 19

Clock_Dividers_Made_Easy - Clock Dividers Made Easy Mohit...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online