fsm_perlscriptfroRTL - fsm_perl: A Script to Generate RTL...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
fsm_perl: A Script to Generate RTL Code for State Machines and Synopsys Synthesis Scripts Clifford E. Cummings Sunburst Design, Inc. ABSTRACT Coding a Verilog RTL model of a state machine requires significant effort to generate an efficient synthesizable implementation. There are a number of different coding styles that can yield different results with varying degrees of efficiency. Because of the effort required to code a Verilog state machine, an engineer typically makes a guess as to which coding style will yield a good implementation and then rarely experiments with other styles after the first model simulates correctly. This paper details a new and highly abbreviated language for coding a state machine and then describes the use of a Perl script called fsm_perl to turn the abbreviated code into a variety of synthesizable models for synthesis experimentation. The fsm_perl also generates an accompanying dc_shell script to synthesize and compare the area and timing of each synthesized implementation.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
SNUG 1999 fsm_perl Rev 1.1 2 1.0 Introduction Coding a Finite State Machine (FSM) is not a difficult task but does involve a fair amount of typing. Efficient Verilog coding styles are well known but which FSM state-encoding style will give the best results is not obvious. The ability to easily generate different Verilog FSM designs and the accompanying synthesis scripts was the reason fsm_perl was developed. Fsm_perl is a freely available Perl script designed to make Finite State Machine (FSM) coding, experimentation and synthesis easy and efficient. Instructions on how to download fsm_perl from the Sunburst Design web site are included at the end of this paper. Figure 1 shows the basic fsm_perl design flow. An fsm_perl source file is coded using any text editor, and then the source file is compiled using the fsm_perl command. Fsm_perl generates two files, the synthesizable Verilog source code file and a Synopsys synthesis script. The Synopsys synthesis script can then be run using dc_shell to read and compile the Verilog FSM code, produce a Verilog gate-level netlist, produce the corresponding SDF timing file and an area/timing report file. Figure 1 - fsm_perl Design Flow module fsm1 (. ..); ... endmodule foreach (. ..) { ... } Verilog FSM file Synopsys synthesis script fsm_perl script fsm1.v fsm1.scr fsm_perl <options> fsm1 dc_shell -f fsm1.scr fsm_perl source code IDLE :: . .. BBUSY:: . .. ... fsm1
Background image of page 2
SNUG 1999 fsm_perl Rev 1.1 3 2.0 Basic fsm_perl Syntax The fsm_perl syntax was designed to make FSM coding simple, compact and easily interpreted; indeed, the fsm_perl syntax was intended to be easier to read and maintain than an equivalent Verilog source file for the same FSM. To this end, the basic fsm_perl syntax largely revolves around triplets to describe state diagram transition arcs.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/20/2010 for the course CEDT 601 taught by Professor Ypr during the Spring '00 term at Indian Institute of Technology, Kharagpur.

Page1 / 20

fsm_perlscriptfroRTL - fsm_perl: A Script to Generate RTL...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online