5_pdfsam_Lecture4_7Updated-04052010

5_pdfsam_Lecture4_7Updated-04052010 - – Finally the 2’s...

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eneral architecture and operation General architecture and operation Example: 01001010 -> 10110110 01001010 -> 11111111+1 – 01001010 = 10110101 + 1 = 10110110 – Write down bits from right until a 1 is encountered. Complements all bits there after eneral Operation Flow General Operation Flow – Load 8 bits into 2 74194 (4 bit shift right/left register) – Do a circular shift on the data, inverting bits as necessary
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Unformatted text preview: – Finally, the 2’s complement data will appear at the output after 8 shift operations Parallel Data Out Invert vertQ Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q InvertQ - - - - - - - -0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 2 1 0 0 1 0 0 1 0 1 3 1 1 0 0 1 0 0 1 1 4 0 1 1 0 0 1 0 0 1 5 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 6 1 1 0 1 1 0 0 1 7 0 1 1 0 1 1 0 0 1 8 1 0 1 1 0 1 1 0 1...
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