MIPS Instruction Reference

MIPS Instruction Reference - MIPS Instruction Reference...

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MIPS Instruction Reference This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly language syntax supported by the MIPS assembler. Hyphens in the encoding indicate "don't care" bits which are not considered when an instruction is being decoded. General purpose registers (GPRs) are indicated with a dollar sign ($). The words SWORD and UWORD refer to 32-bit signed and 32-bit unsigned data types, respectively. The manner in which the processor executes an instruction and advances its program counters is as follows: 1. execute the instruction at PC 2. copy nPC to PC 3. add 4 or the branch offset to nPC This behavior is indicated in the instruction specifications below. For brevity, the function advance_pc (int) is used in many of the instruction descriptions. This function is defined as follows: void advance_pc (SWORD offset) { PC = nPC; nPC += offset; } Note: ALL arithmetic immediate values are sign-extended. After that, they are handled as signed or unsigned 32 bit numbers, depending upon the instruction. The only difference between signed and unsigned instructions is that signed instructions can generate an overflow exception and unsigned instructions can not. The instruction descriptions are given below: ADD – Add (with overflow) Description: Adds two registers and stores the result in a register Operation: $d = $s + $t; advance_pc (4); Syntax: add $d, $s, $t Encoding: 0000 00ss ssst tttt dddd d000 0010 0000 ADDI -- Add immediate (with overflow)
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Description: Adds a register and a sign-extended immediate value and stores the result in a register Operation: $t = $s + imm; advance_pc (4); Syntax: addi $t, $s, imm Encoding: 0010 00ss ssst tttt iiii iiii iiii iiii ADDIU -- Add immediate unsigned (no overflow) Description: Adds a register and a sign-extended immediate value and stores the result in a register Operation: $t = $s + imm; advance_pc (4); Syntax: addiu $t, $s, imm Encoding: 0010 01ss ssst tttt iiii iiii iiii iiii ADDU -- Add unsigned (no overflow) Description: Adds two registers and stores the result in a register Operation: $d = $s + $t; advance_pc (4); Syntax: addu $d, $s, $t Encoding: 0000 00ss ssst tttt dddd d000 0010 0001 AND -- Bitwise and Description: Bitwise ands two registers and stores the result in a register Operation: $d = $s & $t; advance_pc (4); Syntax: and $d, $s, $t Encoding: 0000 00ss ssst tttt dddd d000 0010 0100 ANDI -- Bitwise and immediate Description: Bitwise ands a register and an immediate value and stores the result in a register Operation: $t = $s & imm; advance_pc (4); Syntax: andi $t, $s, imm Encoding: 0011 00ss ssst tttt iiii iiii iiii iiii BEQ -- Branch on equal
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Description: Branches if the two registers are equal Operation: if $s == $t advance_pc (offset << 2)); else advance_pc (4); Syntax: beq $s, $t, offset Encoding: 0001 00ss ssst tttt iiii iiii iiii iiii BGEZ -- Branch on greater than or equal to zero
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This note was uploaded on 04/20/2010 for the course CS 102 taught by Professor Kp during the Spring '10 term at Jaypee University IT.

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MIPS Instruction Reference - MIPS Instruction Reference...

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