Datapath_control

Datapath_control - MIPS32architecture...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
1 MIPS 32 -architecture 32 bit load-store architecture 32 GPRs (32 bit) named as R0. .R31 32  FPRs  (64  bit)  which  can  hold  single  precison(32  bit)  or  dbl  precison  (64  bit)  floating point numbers. Few  special  registers  can  be  transferred  to  GPRs & vice versa. The register R0 always contains 0.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 Data types Byte, Half word (16 bit), Word (32 bit),  Double word (64 bit) for integers. 32 bit single precision or 64 bit double  precision for floating point numbers Byte, half word are loaded in to GPRs  with either 0 or sign bit replicated to fill  the 32 bit GPRs.
Background image of page 2
3 Addressing modes MIPS  has  immediate  and  displacement  with 16 bit fields. Register indirect is accomplished by placing 0 in the displacement field. Absolute/direct  addressing  mode  is accomplished  by  using  register  R0  as  base address. It  uses  a  mode  bit  that  allows  s/w  to  select either Big endian or little endian.
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 Instruction format . op rs rt Offset(16 bit immediate value) 6 bits 5 bits 5 bits 16 bits op rs rt rd funct shamt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R-Format I-Format op Address (Jump target) 6 bits 26 bits J-Format
Background image of page 4
5 Conventions used x,y z indicates that z should be transferred  to x and y. n  means transfer a n bit entity. [R4] 0  –sign bit of R4. [R4] 24. .31  yields LSB of R3. Mem  is used as an array that stands for main  memory. A superscript is used to replicate a field. 0 30   represents a field of 30 0’s. ##  is used to concatenate two fields.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
6 Few Instructions of MIPS ld/lw/lb/lbu/lh sd/sw/sh/sb add/sub/and/slt/or j/jal/jalr/beqz/bne Etc.
Background image of page 6
7 MIPS implementation Simplified to contain only arithmetic-logic instructions:   add, sub, and, or, slt add $t1, $t2, $t3 memory-reference instructions:   lw, sw lw $t1, offset_value($t2) control-flow instructions:   beq, j beq $t1, $t2, offset
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
8 High-level abstract view of  fetch/execute  implementation use the program counter (PC) to read instruction address fetch  the instruction from memory and increment PC use fields of the instruction to select registers to read execute  depending on the instruction repeat… Implementing MIPS: the  Fetch/Execute Cycle Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address
Background image of page 8
9 Overview: Processor  Implementation Styles Single Cycle perform each instruction in 1 clock cycle clock cycle must be long enough for slowest instruction; therefore, disadvantage: only as fast as slowest instruction Multi-Cycle break fetch/execute cycle into multiple steps perform 1 step in each clock cycle
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/20/2010 for the course CS 102 taught by Professor Kp during the Spring '10 term at Jaypee University IT.

Page1 / 54

Datapath_control - MIPS32architecture...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online