chapter7 - Integrated Integrated Circuits Circuits A Design...

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© Digital Integrated Circuits 2nd Sequential Circuits Integrated Integrated Circuits Circuits A Design A Design Perspective Perspective Designing Sequential Designing Sequential Logic Circuits Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic November 2002
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© Digital Integrated Circuits 2nd Sequential Circuits Sequential Logic Sequential Logic 2 storage mechanisms • positive feedback • charge-based COMBINATIONAL LOGIC Registers Outputs Next state CLK Q D Current State Inputs
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© Digital Integrated Circuits 2nd Sequential Circuits Naming Conventions Naming Conventions In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edge- triggered elements flip-flops This leads to confusion however
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© Digital Integrated Circuits 2nd Sequential Circuits Latch versus Register Latch versus Register Latch stores data when clock is low D Clk Q D Clk Q Register stores data when clock rises Clk Clk D D Q Q
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© Digital Integrated Circuits 2nd Sequential Circuits Latches Latches In clk Out Positive Latch CLK D G Q stable follows In Negative Latch CLK D G Q stable follows In
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© Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Design Latch-Based Design N latch is transparent when φ = 0 P latch is transparent when φ = 1 N Latch Logic Logic P Latch φ
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© Digital Integrated Circuits 2nd Sequential Circuits Timing Definitions Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK D Q
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© Digital Integrated Circuits 2nd Sequential Circuits Characterizing Timing Characterizing Timing Clk D Q t C 2 Q D Q t C 2 Q t D 2 Q Register Latch
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© Digital Integrated Circuits 2nd Sequential Circuits Maximum Clock Frequency Maximum Clock Frequency FF’s LOGIC t p,comb φ Also: t cdreg  + t cdlogic  > t hold t cd : contamination delay  =  minimum delay t clk-Q  + t p,comb  + t setup  = T
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© Digital Integrated Circuits 2nd Sequential Circuits Positive Feedback: Bi- Stability Stability V i1 V o2 V o2 = V i 1 V o1 = V i 2 V i1 A C B V V i1 =V V o1 V i2 V i2 o1
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© Digital Integrated Circuits 2nd Sequential Circuits Meta-Stability Meta-Stability Gain should be larger than 1 in the transition region A C d B V i2 5V o1 V i1 5 V o2 A C B V 5 V o2
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© Digital Integrated Circuits 2nd Sequential Circuits Writing into a Static Latch Writing into a Static Latch CLK CLK CLK D Q D CLK CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal,  that distinguishes between the transparent and opaque states
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© Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latches Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0 D Q 0 CLK 1 D Q In Clk Q Clk Q + = In Clk Q Clk Q + =
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© Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latch Mux-Based Latch CLK CLK CLK D Q
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This note was uploaded on 04/22/2010 for the course ECE ECE 165 taught by Professor Buckwalter during the Spring '09 term at UCSD.

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chapter7 - Integrated Integrated Circuits Circuits A Design...

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