vhdl_lab_luebs - ECE201 VHDL Lab Synthesis and Simulation...

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ECE201 VHDL Lab: Synthesis and Simulation of Branch Predictors John K. Luebs December 20, 2007 1 Introduction In this lab various branch predictors, correlating and non-corellating have been designed in VHDL and then synthesized and simulated with test input. Based on the simulation output we can make some observations about the relative efectivness oF these branch predictors. 2 Predictors Implemented ±our diferent branch predictors were implemented. Actually only two Fundamentally distinct designs were implemented: Non-correlating and correlating. However, 3 correlating predictors with diferent design pa- rameters were implemented. All predictors used lookup tables indexed with 3 address bits. The address bits used were bits 2 through 4. The predictors implemented were: 1. A 2-bit branch predictor 2. A 2-bit correlating branch predictor with 2 bits global history or (2 , 2) predictor 3. A 1-bit correlating branch predictor with 1 bit global history or (1 , 1) predictor 4. A 1-bit correlating branch predictor with 3 bits global history or (3 , 1) predictor. 3 Test Vectors Two sets oF test vectors were used For simulation. The ²rst set was that given in the assignment. The second set was one that was generated to simulate a typical scenario with a contrived example oF correlated branches. 3.1 Correlating Test Vectors The Corellating test vectors were generated with a simple python script containing a list oF addresses and directions. The script simply output a vector ²le with the appropriate transitions oF Addr and Dir signals. The test vectors are intended to simulate a loop based on the example presented on page 202 oF the text book. It starts out with 2 taken initial branches and then goes into a “loop.” The loop consists oF two branches that alternate in direction on each iteration oF the loop, together. The ²rst branch is taken iF and only iF the second branch is taken. The branch aFter that is repeatedly taken and is used to simulate a loop condition. On the last part oF the vectors, that loop condition branch is not taken and then an additional branch that was taken in the beginning is also not taken. 1
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4 VHDL Design The branch predictor design in VHDL is fairly straightforward. The branch history table is simply an array of bit vectors of n -bits each, where n is the number of “bits” of the predictor. The state machine is clocked and synchronized by the rising edge of the Cmd line, which acts as a clock. The user must setup the address and direction and then can clock them in with a rising edge on Cmd . In order to read data correctly the user must simply setup the requested address. The only constraint is that the address be setup given the timing constraints before bringing Cmd low, if Cmd is being used as an “input” strobe for the reader. In our test vectors we are doing a functional simulation and, while we setup for the rising edge we do not
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vhdl_lab_luebs - ECE201 VHDL Lab Synthesis and Simulation...

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