CS 232
Practice Exam 2: Solutions
Fall 2009
1.
Virtual Memory and Cache (30 points)
:
A byte addressable memory system has the following specifications: 40bit virtual addresses, 32bit
physical addresses, twolevel cache, 32bit bus with a 1 cycle latency between L2 cache and memory,
interleaved memory with two banks, each with a 10 cycle latency. The TLB and caches have the
following specifications:
TLB
L1 cache
L2 cache
Hit time
2 cycles
1 cycle
15 cycles
Hit rate
99%
75%
95%
(a) If the page size is 512 bytes, fill in the sizes of the VPN and PPN fields:
Page offset = log
2
512 = 9 bits. Hence
VPN =
40

9 = 31
bits, PPN =
32

9 = 23
bits
(b) The directmapped L1 cache holds 16 KB of data in 512 blocks, and has a writethrough
policy.
How many bits does it take to implement this cache?
Show your work for partial
credit!
Solution
:
The block size is
16
Kbytes
512
blocks
= 32 bytes per block.
Hence, the block offset is
log
2
32 = 5 bits.
Since the cache is directmapped, the number of sets is equal to the number of blocks i.e.,
512. Thus the index is log
2
512 = 9 bits. Hence, the tag is 32

9

5 = 18 bits long.
Since the cache is writethrough, there are no dirty bits.
Thus each block stores data,
tag and valid bits.
Hence, the total number of bits required to implement the cache is
512
×
(32
×
8 + 18 + 1)
(c) The L2 cache has the same block size as the L1 cache but holds 256 times as much data.
It has a writeback policy, full LRU, and can be implemented using 4296 KB. What is the
associativity of the L2 cache? Show your work for partial credit!
Solution
: Suppose the cache is 2
k
way associative. Since it has the same block size as L1 but
holds 2
8
times more data, it must have 2
8
times as many blocks. Thus, it has 2
8
/
2
k
= 2
8

k
as many sets, so the index field would be 8

k
bits longer (i.e., 17 +
k
bits long) and the tag
would be 8

k
bits shorter (i.e., 10 +
k
bits long). Also, this cache has dirty bits.
To implement full LRU, the cache needs
m
=
log
2
(2
k
)!
LRU bits per set. Thus, the total
number of bits to implement this cache is 2
8
×
512
×
(32
×
8 + 10 +
k
+ 1 + 1) + 2
8

k
.m
=
4296
×
1024
×
8 bits. We can solve this for
k
and obtain the associativity
2
k
.
The problem on the exam will not involve such icky math, and you can
always leave your
answer as expressions
. Do not simplify unless you absolutely have to.
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 Fall '08
 Garzaran
 Central processing unit, CPU cache, Cache algorithms, Memory management unit

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