1
Department of Electrical Engineering
McGill University
ECSE 221 Introduction to Computer Engineering I
Final Examination
Thursday, April 21
st
, 2005
2:00pm
Examiner:
Prof. F.P. Ferrie
Associate Examiner: Prof. J. Clark
Instructions:
Answer ALL questions in the examination booklet provided, showing all of your work.
Calculators are permitted, but they must be the Faculty standard.
All questions are equally
weighted.
Question 1
a)
The IEEE double precision format has a 52bit mantissa.
Determine the precision and
range of real numbers that can be represented using this format.
[2 points]
b)
Divide 10100111
2
by 111
2
using binary long division.
[2 points]
c)
Encode the number –1.42 x 10
19
using IEEE754 single precision floatingpoint format.
Express your answer an 8digit hexadecimal number.
[2 points]
d)
Prove that the contents of two binary variables, A and B, can be exchanged by the
following sequence of operations: A=XOR(A,B)
B=XOR(A,B)
A=XOR(A,B) [2 points]
e)
Determine the minimal canonical forms corresponding to the following sum of products
form:
(5,8,9,10,12,13,14)
A
,
B
,
C
,
D
∑
[2 points]
Question 2
J
C
K
S
R
Q
Q
J
C
K
S
R
Q
Q
J
C
K
S
R
Q
Q
+5V
+5V
+5V
+5V
Clr
Clk
Mode
Q2
Q1
Q0
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The circuit shown on the previous page is comprised of rising edgetriggered JK flipflops and
combinational logic.
At T=0, it is initialized to <Q2=0, Q1=0, Q0=0> by applying a reset pulse
to the asynchronous Clr input.
Under normal operation, the circuit will count in one of two
sequences depending on whether the Mode input is 1 or 0.
Answer the following questions:
a)
Determine the next state equations corresponding to Q2, Q1, and Q0 respectively.
Use
these equations to then determine the state transition table corresponding to this circuit.
[3 points]
b)
Assume that each gate has Tpd=0.1nS and that gates with inverted inputs (indicated by a
bubble on the inverted input) have Tpd=0.15nS.
The timing parameters for flipflops Q2
and Q0 are identical, Tpd=1nS, Th=0.1nS, and Tsu=0.25nS.
Flipflop Q1 has
Tpd=1.5nS, Th=0nS, and Tsu=0.4nS.
Determine the maximum frequency of operation
for this circuit.
Next, produce a detailed timing diagram showing three clock transitions
beginning with <Q2=0, Q1=0, Q0=0> and Mode=0.
[3 points]
c)
Show how this circuit can be reimplemented with a readonly memory (ROM) and 3 D
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 Winter '09
 F.PFERRIE
 Assembly Language, MIPS architecture

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