Activity15 Soln - SOLUTION In-Class Activity #15 3/23/2001...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
ECSE-2660 Computer Architecture, Networks, & Operating Systems, Spring 2001 Page 1 of 2 SOLUTION In-Class Activity #15 3/23/2001 10:05 AM Activity 15.1 1. Memory Organization 1a. What is the purpose of the Translation Look-Aside Buffer? Is it SRAM or DRAM? It is SRAM. It allows determination of the physical address of frequently used items without a memory reference to the page table in a virtual memory environment. 1b. Do two-level page tables (Outer and Inner) speed up virtual memory? Why is it used? This design slows down memory access because of the extra look up. The impact on speed is minimal because of the low frequency of double page faults. A single-level page table may use up too much primary storage. 1c. Why is the hit rate of a cache with higher associativity typically higher than that of a direct-mapped cache of the same size? Why is an associative cache more expensive? Advantage: Associative caches don’t have to evict recently used blocks because of an index conflict. Several words
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/25/2010 for the course ECSE ecse-2340 taught by Professor Wozny during the Spring '09 term at Rensselaer Polytechnic Institute.

Page1 / 2

Activity15 Soln - SOLUTION In-Class Activity #15 3/23/2001...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online