{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Homework07-sol

# Homework07-sol - 5:44 AM Homework#07(Solution 5:44 AM 1(15...

This preview shows pages 1–2. Sign up to view the full content.

3/26/03 5:44 AM ECSE-2660 Computer Architecture, Networks, & Operating Systems, Spring 2002 Page 1 of 4 Homework #07 (Solution) 3/26/2003 5:44 AM 1. (15 points) Problem 6.23 from the text (the worst ordering will have two stalls). lw \$3, 0(\$5) add \$7, \$7, \$3 #requires stall on #3 lw \$4, 4(\$5) add \$8 \$8, \$4 #requires stall on \$4 add \$10, \$7, \$8 sw \$6, 0(\$5) beq \$10, \$11, Loop Grading: 3pts for trying, +6 pts for rearranging for each stall. 2. (15 points) Problem 6.24 from the text. 36 beqd \$1, \$3, 8 40 sub \$10 \$4, \$8 #delay slot, always executed Grading: 5pts for trying, +10pts for sub after beqd, +7pts for any code that works using beqd. 3. (20 points) Consider a computer system that is organized as shown below: CPU Cache Main Memory (DRAM) Bus The following table summarizes some relevant parameters relating to the memory system: Calculate the average memory access time assuming that the main memory (DRAM) can be operated at its maximum possible speed, i.e. 80ns per word 60% of the time, and at 165ns per word 40% of the time. Hint: Make a tree diagram. Cache (SRAM) Access Time 20ns DRAM Access Time – best case (see comment below) 80ns DRAM Cycle Time – worst case (see comment below) 165ns Cache Hit Rate 98% Cache Block Size 4 words

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}