Homework08-sol - Homework #08 (Solution) 3/25/2003 12:00 PM...

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ECSE-2660 Computer Architecture, Networks, & Operating Systems, Spring 2003 Page 1 of 6 Homework #08 (Solution) 3/25/2003 12:00 PM Memory Configurations 1. ( 15 points ) Do question 7.11 in P&H text. Assume that it takes one clock cycle to send the address to the main memory. The miss penalty is the time to transfer one block from main memory to the cache. a) Configuration (a) requires 16 main memory accesses to retrieve a cache block and words of the block are transferred 1 at a time. Miss penalty = 1 + 16x10 + 16x1 = 177 clock cycles b) Configuration (b) requires 4 main memory accesses to retrieve a cache block and words of the block are transferred 4 at a time. Miss penalty = 1 + 4x10 + 4x1 = 45 clock cycles c) Configuration (c) requires 4 main memory accesses to retrieve a cache block and words of the block are transferred 1 at a time. Miss penalty = 1 + 4x10 + 16x1 = 57 clock cycles Grading instructions: 5pts for each correct miss penalty, 3pts for partial answer (i.e. correct number of memory accesses but wrong number of words fetched at one memory access) at each configuration, 3pts for trying Cache addresses 2. ( 20 points ) Consider a cache for a computer with 32-bit addresses. The memory system is byte addressable. The cache holds 1024 Kbytes of data. Cache A is direct mapped, and has a block size of 4 bytes (1 word). Cache B is direct mapped, and has a block size of 8 bytes (2 words). The tag and the cache index together have just enough bits to identify each block. The following table lists a series of successive memory references as hex word addresses. Label each reference as a hit (H) or a miss (M), depending upon cache configuration (Cache A or Cache B) and fill in the value of the cache index and the tag for each memory reference. Initially all the valid bits are set to zero. Hint: First calculate the cache index for each address by figuring out which bits of a 32-bit address represent what. Think about what happens when the same index appears again… For cache A, we need 18bits of cache index in order to index 1024 Kbytes / 4 blocks of data. Also, we need 2bits as the byte offset within each word. So, the tag in cache A is composed of 32 – (18+2) = 12bits. CACHE A 32-bit byte address 12-bit tag 18-bit cache index byte offset Hit/ Miss 0012 762A 0000 0000 0001 0 0 1 0010 0111 0110 0010 10 2 7 6 2 2 10 M 0052 0A28 0000 0000 0101 0 0 5 0010 0000 1010 0010 10 2 0 A 2 2 00 M 0012 7629 0000 0000 0001 0 0 1 0010 0111 0110 0010 10 2 7 6 2 2 01 Hit 001A 7629 0000 0000 0001 0 0 1 1010 0111 0110 0010 10
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This note was uploaded on 04/25/2010 for the course ECSE ecse-2340 taught by Professor Wozny during the Spring '09 term at Rensselaer Polytechnic Institute.

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Homework08-sol - Homework #08 (Solution) 3/25/2003 12:00 PM...

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