EE-638 hw#3 - EE-638 ADVANCED VLSI DESIGN HOMEWORK #3...

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EE-638 ADVANCED VLSI DESIGN HOMEWORK #3 ENGİN AFACAN
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A COMPARISON OF FFT APPLICATIONS IMPLEMENTED BY USING DSP,FPGA AND ASIC The increasing demand for high-speed digital applications has been driving to a huge usage of low-cost digital signal processing devices, especially in consumer electronics. This rapid increase , along with the different computational capabilities of such devices, makes difficult the selection of the best component for a given application, namely the item that is able to meet given design specifications at the lowest cost. This issue is further stressed by a certain lack of univocal techniques for the characterization of computing devices. However, in spite of theoretical limitations and major technological differences, the performances of different digital signal processing devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs),Application Specific Integrated Circuits (ASICs), and Field Programmable Gate Arrays (FPGAs) need to be assessed and compared so that a designer can make an optimal component selection.[1] Figure 1.Clock frequencies for FFT ASIC,FPGA and DSP In Fig. 1 the clock frequency ranges of different FFT designs are compared by means of a bar diagram. As the figure shows,DSP has the maximum clock frequency for FFT applications. In fact, the working clock frequency of any FPGA FFT core is usually much lower than the nominal maximum frequency of the chip employed for the implementation.[1]
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Figure.2 Real Time Band Width A more objective performance analysis is shown in Fig.2, in which the RTBW values related to the computation of a 1024-point complex FFT processed with different models of FPGAs, DSPs, and ASICs, are displayed. Each bar represents the performance range of the corresponding class of devices. Quite obviously, dedicated ASICs outperform any other technology . Furthermore, their maximum clock frequency (i.e. 133 MHz) is considerably lower than that of fastest DSP considered (i.e. 300 MHz). By using the more efficient FFT algorithm for a given kind of processors, FPGA cores are characterized by a RTBW that ranges from about 5 MHz to about 12 MHz. Therefore, FPGA cores’ maximum RTBW is slightly higher than the maximum value achievable by typical DSP implementations even though, as stated previously, only FPGA fixed-point implementations have been considered in the current analysis. Consider also that FPGA performance is strongly related to the features of the software employed for the synthesis.[1]
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Hipar-DSP16 Hipar-DSP4 Parallel Data Paths 16 parallel paths 4 parallel paths Technology 0,35 um CMOS 3LM standard cell with full custom memories 0,6 um CMOS 2LM standard cell with full custom memories Transistors 4.3 million 1.2 million Area 200mm² 250mm² Power Consumption 8 watt 5 watt Clock frequency 100MHz 80MHz Table 1. A FFT application features that implemented on DSP Since the best performance ,in terms of maximum processing speed, are generally
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EE-638 hw#3 - EE-638 ADVANCED VLSI DESIGN HOMEWORK #3...

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