06a Introduction to CUDA (NVIDIA)

06a Introduction to CUDA (NVIDIA) - Introduction to CUDA...

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Introduction to CUDA
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© NVIDIA Corporation 2008 GPU Performance History GPUs are massively multithreaded many-core chips Hundreds of cores, thousands of concurrent threads Huge economies of scale Still on aggressive performance growth
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© NVIDIA Corporation 2008 CUDA CUDA is industry-standard C Write a program for one thread Instantiate it on many parallel threads Familiar programming model and language CUDA is a scalable parallel programming model Program runs on any number of processors without recompiling
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© NVIDIA Corporation 2008 GPU Sizes Require CUDA Scalability GPU Interconnection Network SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Texture Unit Tex L1 Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C -Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Tex L1 DRAM ROP L2 DRAM ROP L2 DRAM ROP L 2 DRAM ROP L2 DRAM ROP L2 DRAM ROP L2 Bridge System Memory Work Distribution Host CPU SM SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU 128 SP Cores GPU Interconnection Network SMC Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C- Cache SFU SFU Texture Unit Tex L 1 Geometry Control er SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU Tex L1 DRAM ROP L2 DRAM ROP L2 Bridge Work Distribution Host CPU SM SP Shared Memory SP SP SP SP SP SP SP I-Cache MT Issue C-Cache SFU SFU 32 SP Cores GPU Bridge System Memory Work Distribution ` SM C ` SP D P SP SP SP SP SP SP SP I - C ache M T Is ue C - C ache SFU SFU Shar ed M em or y Textur e U nit Tex L 1 SP D P SP SP SP SP SP SP SP
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06a Introduction to CUDA (NVIDIA) - Introduction to CUDA...

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