# hw7_sol - CDA 3101 Assignment 7 Due in class on Friday Dec...

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CDA 3101 Assignment 7 Due in class on Friday, Dec. 4 Turn hardcopy in class, stapled, with your name and “CDA 3101 Assignment 7” clearly written on it. Assignments submitted after Dec. 4, 12:35 pm but before Dec. 7, 12:35 pm will be considered one day late. 1. a. (2 points) Problem 4.12.1b from the textbook(4 th edition). Pipelined: 200ps Single-Cycle: 800ps b. (2 points) Problem 4.12.2b from the textbook(4 th edition). Pipelined: 1000ps Single-Cycle: 800ps c. (2 points) Problem 4.12.3b from the textbook(4 th edition) IF, new cycle time = 190 ps d. (2 points) Problem 4.12.6b from the textbook(4 th edition) Multi-cycle / pipeline = 0.30 × 5 + 0.70 × 4 = 4.30 Single-cycle/pipeline = 800/200 = 4.00 2. a. (3 points) Name and describe the 3 types of pipeline hazards that can occur. Briefly explain a situation when the hazard could occur in the MIPS processor. Structural Hazard: Occurs when hardware doesn’t have the resources to handle some combination of instructions. ..this never occurs in the MIPS pipeline because the instruction and data memories are separated and the register file is fast enough to be read and written to in half a clock-cycle (and thus can be written in the WB stage during the first half of the clock and read in the ID stage during the second half of the clock). Data Hazard: Occurs when some produced value is needed before the processor/memory state has been updated. This in MIPS mainly refers to registers, which are read in the 2 nd cycle but updated in the 5 th , thus leaving cycles where an add instruction (like the one below) could be waiting until the WB stage to write to a register \$t0, while the sub instruction after the “add” has already read the old (incorrect) value in the ID stage. Control Hazard: Only occurs on instructions that change the PC, such as branch instructions (or

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hw7_sol - CDA 3101 Assignment 7 Due in class on Friday Dec...

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