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Power Optimization of 4x4-Bit Pipelined Array Multiplier Author: Yaseer A. Durrani Supervisor: Teresa Riesgo Universidad Politécnica de Madrid División de Ingeniería Electrónica Escuela Técnica Superior de Ingenieros Industriales (Oct, 2004)
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Power Optimization of 4x4-Bit Pipelined Array Multiplier 2 Abstract In this paper, we presented a feasible method of pipelined 4x4-bit array multiplier and evaluated the results by the flexible estimation methods, gate simulation or register- annotated simulation. The multiplier architecture is for low power and high speed applications. The experimental results indicated that this internal optimization reduced the power consumption of this circuit effectively. 1. Introduction As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amount of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in today’s system design. The need of low power VLSI systems arises from two main forces. First, with the steady growth of operating frequency and processing capacity per chip, large current has to be delivered and the heat due to large power consumption must be removed by proper cooling techniques. Second, battery life in portable electronic devices is limited. Low power design directly leads to prolonged operation time in these portable devices. Multiplication is a fundamental operation in most signal processing algorithms [1]. Multipliers have large area, long latency and consume considerable power. Therefore, low power multiplier design has been an important part in low power VLSI system design. There has been extensive work on low power multipliers at technology, physical, circuit and logic levels. These low-level techniques are not unique to multiplier modules and they are generally applicable to other types of modules. The characteristics of arithmetic computation in multipliers are not considered well. Moreover, power consumption is directly related to data switching patterns. However, it is difficult to consider application-specific data characteristics in low-level power optimization. This dissertation addresses high-level optimization techniques for low power multipliers. High-level techniques refer to algorithm and architecture level techniques that consider multiplication’s arithmetic features and input data characteristics. The main research hypothesis of this work is that high-level optimization of multiplier design produces more power-efficient solutions than optimization only at low-levels. Specifically, we consider how to optimize the internal algorithm and architecture of multipliers and how to control active multiplier resource to match external data characteristics. The primary objective is power reduction with small area and delay overhead. By using algorithms or architecture, it is even possible to achieve both power
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