3765791745 - CEG/EE 260 NAME 1(20 Show the(1 an SR latch...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
CEG/EE 260 Sample Final Fall 2007 NAME: 1. (20%) Show the internal logic diagrams of the following circuits. (1) an SR latch (not S-R latch) with NAND gates, (2) a positive edge-triggered D flip-flop, In the exam, you need to give the internal circuit of the D-latch and the S-R latch. (3) a half adder, C S R Q Q C Q Q C D Q D Q 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2. (20%) For the circuit shown and the given clock, draw the waveforms that appear at A, B, and C. Assume that all the flip-flops are initially cleared and propagation delay can be ignored. Input Equations: Da=(Qa’+Qc’)’=Qa*Qc Tb=Qc’ Jc=Qc’ exclusive or Qb’ Kc=Qb’ State Table: Current Sate Next State Flip Flop Inputs Qc Qb Qa Qc Qb Qa Da Tb Jc Kc 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 2 CLK Q CLK Q T D CLK Q CLK Q J K Q Q A B C A B C
Background image of page 2
(20 points) Draw the logic diagram for a 4-bit register with mode selection inputs S0 and S1. The register is to be operated by the following function table: 4.(20%) The two numbers A and B are both in 7-bit signed two’s-complement
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/03/2010 for the course CEG 260 taught by Professor Staff during the Spring '08 term at Wright State.

Page1 / 5

3765791745 - CEG/EE 260 NAME 1(20 Show the(1 an SR latch...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online