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4055755329 - CEG/EE 260 Dr Sridhar Ramachandran Lab 2 Lab 2...

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CEG/EE 260 Lab 2 Dr. Sridhar Ramachandran Lab 2: Combinational Design (a.k.a The Car Speed Warning Circuit lab) CEG/EE 260 PURPOSE The purpose of this laboratory project is to introduce students to the synthesis of a digital device consisting exclusively of combinational functionality. In this lab, we will start with a natural lan- guage description of a device for which will then be designed, simulated, tested, and imple- mented. In week one of this lab, students will implement a simple car speed warning device and implement the device using a multi-level AND-OR-NOT logic implementation. In week two of this lab, students will implement this same device using a multi-level NAND implementation. CAR SPEED WARNING CIRCUIT Consider a simple car speed warning device that has two 2 bit inputs as shown in the diagram below. The first set of 2 bit inputs [a, b] are indicative of the speed limit restrictions in-effect. There are three possible speed limit values: 45, 55 or 65MPH as shown in the table below; the driver provides these inputs. The second set of 2 bit inputs [c, d] is obtained from the speed sen- sor of the automobile. There are four possible values of the car speed sensor: under 45, between 46 and 55, between 56 and 65 and over 65 MPH.
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