2936397525 - Chapter 6 Programmable Logic Devices Meilin...

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Unformatted text preview: Chapter 6 Programmable Logic Devices Meilin Liu Department of Computer Science Wright State University Homepage: http://www.wright.edu Email: meilin.liu@wright.edu CEG 260, Meilin Liu 2 Outline Part 1 Combinational Logic Circuit Design Design Procedure o The major design steps: specification, formulation, optimization, technology mapping, and verification Technology Mapping o Mapping from AND, OR, and NOT to other gate types, such as NAND, NOR, and Programmable logic devices Verification o Does the designed circuit meet the specifications? Part 2 - Programmable Implementation Technologies Programmable Logic Arrays, Programmable Array Logic, Read- Only Memories o Technology mapping to programmable logic devices CEG 260, Meilin Liu 3 Overview Why programmable logic? Programmable logic technologies Programmable Logic Array (PLA) Programmable Array Logic (PAL) Read-Only Memory (ROM) CEG 260, Meilin Liu 4 Why Programmable Logic? Facts: It is most economical to produce an IC in large volumes Many designs required only small volumes of ICs Need an IC that can be: Produced in large volumes Handle many designs required in small volumes A programmable logic part can be: made in large volumes programmed to implement large numbers of different low-volume designs CEG 260, Meilin Liu 5 Programmable Logic - Additional Advantages...
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2936397525 - Chapter 6 Programmable Logic Devices Meilin...

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