ISA-2 - 4-1Principles of Computer Architecture

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Unformatted text preview: 4-1Principles of Computer Architecture 2005ParallelismInstruction-level parallelismpipelinesuperscalelatency issuesProcessor-level parallelismarray/vector of processors (1 control unit, limited application)multiprocessor (multiple CPUs, common memory)multicomputer (multiple CPUs, each with own memory)4-2Principles of Computer Architecture 2005Instruction-Level Parallelism4-3Principles of Computer Architecture 2005Pipelining allows a trade-off between latency (how long it takes to execute an instruction), and processor bandwitdh (how many MIPS the CPU has).If:Cycle time= T nsecN stages in the pipelineSo Latency= NxT nsec and Bandwidth= 1000/T MIPS 4-4Principles of Computer Architecture 2005Instruction PipeliningSimilar to assembly line in manufacturing plants:Products at various stages can be worked on simultaneouslyPerformance improvedFirst attempt: 2 stagesFetchExecution4-5Principles of Computer Architecture 2005PrefetchFetch accessing main memoryExecution usually does not access main memoryCan fetch next instruction during execution of current instructionCalled instruction prefetch or fetch overlapIdeallyinstruction cycle time would be halved(if durationF= durationE)4-6Principles of Computer Architecture 2005Improved Performance (1)But not doubled in reality, why?Fetch usually shorter than executionPrefetch more than one instruction?Any jump or branch (branching) means that prefetched instructions are not the required instructionse.g., ADD A, BBEQ NEXTADD B, CNEXTSUB C, D4-7Principles of Computer Architecture 2005Improved Performance (2)Add more stages to improve performanceReduce time loss due to branching by guessingPrefetch instruction after branching instructionIf not brancheduse the prefetched instructionelsediscard the prefetched instructionfetch new instruction4-8Principles of Computer Architecture 2005Two Stage Instruction Pipeline4-9Principles of Computer Architecture 2005PipeliningMore stages more speedup (the more the merrier)FI: Fetch instructionDI: Decode instructionCO: Calculate operands (i.e. EAs)FO: Fetch operandsEI: Execute instructionsWO: Write resultVarious stages are of nearly equal durationOverlap these operations4-10Principles of Computer Architecture 2005Timing of Pipeline4-11Principles of Computer Architecture 2005Speedup of Pipelining (1)9 instructions6 stagesw/o pipelining: __ time unitsw/ pipelining: __ time unitsspeedup = _____Q: 100 instructions6 stages, speedup = ____Q: instructionskstages, speedup = ____4-12Principles of Computer Architecture 2005Speedup of Pipelining (2) Parameters2200= pipeline cycle time = time to advance a set of instructions one stagek= number of stagesn= number of instructionsAssume no branch, time to execute ninstructionsTk= [k+ (n- 1)]Time to execute ninstructions without pipelining T1= nk4-13Principles of Computer Architecture...
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This note was uploaded on 05/04/2010 for the course CS 333 taught by Professor Alarabi during the Spring '10 term at DeVry Cleveland D..

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ISA-2 - 4-1Principles of Computer Architecture

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