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Mem-Exercise-2 - Exercise Assuming a cache of 4K blocks a...

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Unformatted text preview: Exercise Assuming a cache of 4K blocks, a fourword block size, and 32-bit address, find the total number of sets and the total number of tag bits for caches that are direct mapped, two way and four way set associative, and fully associative. Solution Since there are 16 (=24) bytes per block, a 32-bit address gives 32-4=28 bits to be used for index and tag. 1) direct-mapped: same number of sets as blocks, so 12 bits of index (since 4K), thus total number of tag bits is (2812)x4K=64Kbits. Continued 2)2-way associative: there are 2K sets, and total number of of tag bits is (28-11)x2x2K=34x2K=68Kbits 4-way associative: there are 1K sets, total number of tag bits: (28-10)x4x1K=72Kbits Fully associative: Only one set with 4K blocks, and the tag is 28 bits, so total: 28x4Kx1=112K tag bits Exercise Consider a 3-way set-associative write through cache with an 8 byte blocksize, 128 sets, and random replacement. Assume a 32-bit address. How big is the cache (in bytes)? How many bits total are there in the cache (i.e. for data, tags, etc.). Solution The cache size is 8 * 3 * 128 = 3072 bytes. Each line has 8 bytes * 8 bits/byte = 64 bits of data. A tag is 22 bits (2 address bits ignored, 1 for position of word, 7 for index). Each line has a valid bit (no dirty bit 'cause it is write-through). Each line therefore has 64 + 22 + 1 = 87 bits. Each set has 3 * 87 = 261 bits. There are no extra bits for replacement. The total number of bits is 128 * 261 = 33408 bits. Exercise Assume there are three small caches, each consisting of four one-word blocks. One cache is direct mapped, a second is two-way set associative, and the third is a fully associative. Find the number of misses for each cache organization given the following sequence of block addresses: 0, 8, 0, 6, 8. Solution: direct-mapped Remember: i=j modulo m Address of mem block addressed 0 8 0 6 Block Address 0 6 8 Cache block (0 modulo 4)=0 (6 modulo 4)=2 (8 modulo 4)=0 block after reference 3 Hit Contents of or miss 0 miss miss miss miss Memory[0] Memory[8] Memory[0] Memory[0] Cache 1 2 Memory[6] 8 miss Memory[8] Memory[6] The direct-mapped cache generates five misses for the five accesses. Solution: 2-way set associative Remember: i=j modulo v Address of mem block addressed 0 8 0 6 Block Address 0 6 8 Hit Contents of or miss Set 0 miss miss hit miss Memory[0] Memory[0] Memory[0] Memory[0] Memory[8] Memory[8] Memory[6] Cache Cache set (0 modulo 2)=0 (6 modulo 2)=0 (8 modulo 2)=0 block after reference Set 1 Set 0 Set 1 8 miss Memory[8] Memory[6] The 2-way set associative cache has 4 misses, one less than the direct Solution: Fully associative Remember: One single set of 4 blocks Address of mem block addressed 0 8 0 6 8 Hit or miss Contents of Cache block after reference Block 3 Block 0 miss miss hit miss hit Memory[0] Memory[0] Memory[0] Memory[0] Memory[0] Block 1 Block 2 Memory[8] Memory[8] Memory[8] Memory[8] Memory[6] Memory[6] The fully associative cache has the best performance with only 3 misses. ...
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