10-VIRTUAL_MEMORY

10-VIRTUAL_MEMORY - VIRTUAL MEMORY Overlays A partition...

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Unformatted text preview: VIRTUAL MEMORY Overlays A partition graph for a program with a main routine and three subroutines: Motivations for Virtual Memory Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Multiple processes resident in main memory. Simplify Memory Management Each process with its own address space Allocate more memory to process as needed. Only "active" code and data is actually in memory Provide Protection One process can't interfere with another. because they operate in different address spaces. different sections of address spaces have different permissions. User process cannot access privileged information Virtual memory is stored in a hard disk image. The physical memory holds a small number of virtual pages in physical page frames. mapping between a virtual and a physical memory: A Motivation #1: DRAM a "Cache" for Disk Full address space is quite large: 32-bit addresses: ~4,000,000,000 (4 billion) bytes 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes 80 GB of DRAM: ~ $33,000 80 GB of disk: ~ $110 Disk storage is ~300X cheaper than DRAM storage To access large amounts of data in a cost-effective manner, the bulk of the data must be stored on disk 80 GB: ~$110 1GB: ~$200 4 MB: ~$500 SRAM DRAM Disk Levels in Memory Hierarchy cache virtual memory CPU regs C a c h e Memory disk Register size: speed: $/Mbyte: 32 B 1 ns Cache Memory Disk Memory 100 GB 8 ms $0.001/MB 32 KB-4MB 1024 MB 2 ns 30 ns $125/MB $0.20/MB larger, slower, cheaper DRAM vs. SRAM as a "Cache" DRAM vs. disk is more extreme than SRAM vs. DRAM Access latencies: DRAM ~10X slower than SRAM Disk ~100,000X slower than DRAM Importance of exploiting spatial locality: First byte is ~100,000X slower than successive bytes on disk SRAM DRAM Disk Impact of Properties on Design If DRAM was to be organized similar to an SRAM cache, how would we set the following design parameters? Line size? since disk better at transferring large blocks Large, Associativity? High, to mimimize miss rate back, since can't afford to perform small writes to disk Write through or write back? Write What would the impact of these choices be on: rate low. << 1% miss hit Extremely time match cache/DRAM performance high. ~20ms Must miss latency Very A System with Virtual Memory Examples: workstations, servers, modern PCs, etc. Page Table Virtual Addresses 0: 1: Physical Addresses Memory 0: 1: CPU P-1: N-1: Disk Address Translation: Hardware converts virtual addresses to physical addresses via OS-managed lookup table (page table) Page Faults (like "Cache Misses") What if an object is on disk rather than in memory? Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory current process suspends, others can resume OS has full control over placement, etc. Before fault Page Table Virtual Physical Addresses Addresses CPU Memory After fault Memory Page Table Virtual Addresses CPU Physical Addresses Disk Disk Solution: Separate Virt. Addr. Spaces Virtual and physical address spaces divided into equalsized blocks blocks are called "pages" (both virtual and physical) Each process has its own virtual address space 0 operating system controls how virtual pages as assigned to physical memory 0 VP 1 VP 2 Address Translation PP 2 Virtual Address Space for Process 1: ... Physical Address Space (DRAM) N-1 PP 7 Virtual Address Space for Process 2: 0 VP 1 VP 2 ... PP 10 M-1 N-1 Motivation #3: Protection Page table entry contains access rights information hardware enforces this protection (trap into OS if violation occurs) Page Tables Memory Read? Write? VP 0: Yes No Yes No Physical Addr PP 9 PP 4 XXXXXXX 0: 1: Process i: VP 1: Yes VP 2: No Physical Addr PP 6 PP 9 XXXXXXX Read? Write? VP 0: Yes Yes Process j: VP 1: Yes VP 2: No No No N-1: VM Address Translation Virtual V Address Space Address Space = {0, 1, ..., N1} Physical P = {0, 1, ..., M1} M < N VM Address Translation Parameters P = 2p = page size (bytes). N = 2n = Virtual address limit M = 2m = Physical address limit p p1 virtual page number page offset 0 virtual address n1 address translation m1 p p1 physical page number page offset 0 physical address Page offset bits don't change as a result of translation Page Tables Virtual Page Number Memory resident page table (physical page Valid or disk address) 1 1 0 1 1 1 0 1 0 1 Physical Memory Disk Storage (swap file or regular file system file) Address Translation via Page Table page table base register VPN acts as table index virtual address n1 p p1 virtual page number (VPN) page offset valid access physical page number (PPN) 0 if valid=0 then page not in memory m1 p p1 physical page number (PPN) page offset physical address 0 Page Table Operation Computing Page if Physical Address Table Entry (PTE) provides information about page (valid bit = 1) then the page is in memory. physical page number (PPN) to construct address fault Use if (valid bit = 0) then the page is on disk Page Checking Access Protection rights field indicate allowable access e.g., read-only, read-write, execute-only typically support multiple protection modes (e.g., kernel vs. user) Protection violation fault if user doesn't have necessary permission Integrating VM and Cache VA CPU Translation hit data PA Cache miss Main Memory Most Caches "Physically Addressed" Accessed by physical addresses Allows multiple processes to have blocks in cache at same time Allows multiple processes to share pages Cache doesn't need to be concerned with protection issues Access rights checked as part of address translation Perform Address Translation Before Cache Lookup But this could involve a memory access itself (of the PTE) Of course, page table entries can also become cached Speeding up Translation with a TLB "Translation Lookaside Buffer" (TLB) Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages hit PA TLB Lookup miss Translation data hit Cache VA CPU miss Main Memory Address Translation with a TLB n1 p p1 0 virtual page number page offset virtual address valid tag physical page number . . = . TLB TLB hit physical address tag valid tag data index byte offset Cache = cache hit data Multi-Level Page Tables Given: Level 2 Tables 4KB (212) page size 32-bit address space 4-byte PTE Would need a 4 MB page table! Level 1 Table Problem: 220 *4 bytes ... Common solution multi-level page tables e.g., 2-level table (P6) Level 1 table: 1024 entries, each of which points to a Level 2 page table. Level 2 table: 1024 entries, each of which points to a page Simple Memory System Example Addressing 14-bit virtual addresses 12-bit physical address Page size = 64 bytes 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN (Virtual Page Number) 11 10 9 8 7 6 VPO (Virtual Page Offset) 5 4 3 2 1 0 PPN (Physical Page Number) PPO (Physical Page Offset) Simple Memory System Page Table Only show first 16 entries VPN 00 01 02 03 04 05 06 07 PPN Valid VPN 28 33 02 16 1 0 1 1 0 1 0 0 08 09 0A 0B 0C 0D 0E 0F PPN Valid 13 17 09 2D 11 0D 1 1 1 0 0 1 1 1 Simple Memory System TLB TLB 16 entries 4-way associative TLBT TLBI 9 8 7 6 5 4 3 2 1 0 12 11 10 13 VPN VPO Set 0 1 2 3 Tag 03 03 02 07 PPN Valid 2D 0 1 0 0 Tag 09 02 08 03 PPN Valid 0D 0D 1 0 0 1 Tag 00 04 06 0A PPN Valid 34 0 0 0 1 Tag 07 0A 03 02 PPN Valid 02 1 0 0 0 Simple Memory System Cache Cache 16 lines 4-byte line size Direct mapped CT 11 10 9 8 7 6 5 4 CI 3 2 1 CO 0 PPN Idx 0 1 2 3 4 5 6 7 Tag 19 15 1B 36 32 0D 31 16 Valid 1 0 1 0 1 1 0 1 B0 99 00 43 36 11 B1 11 02 6D 72 C2 B2 23 04 8F F0 DF B3 11 08 09 1D 03 Idx 8 9 A B C D E F Tag 24 2D 2D 0B 12 16 13 14 PPO Valid 1 0 1 0 0 1 1 0 B0 3A 93 04 83 B1 00 15 96 77 B2 51 DA 34 1B B3 89 3B 15 D3 Address Translation Example #1 Virtual 13 12 Address 0x03D4 TLBT 11 10 9 8 7 TLBI 6 5 4 3 2 1 0 VPN VPN ___ VPO TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Physical Address CT CI 7 6 5 4 3 2 1 CO 0 11 10 9 8 PPN Offset ___ CI___ CT ____ Hit? __ PPO Byte: ____ Address Translation Example #2 Virtual 13 Address 0x0B8F TLBT TLBI 9 8 7 6 5 4 3 2 1 0 11 10 12 VPN VPN ___ VPO TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Physical Address CT 11 10 9 8 7 6 5 4 CI 3 2 1 CO 0 PPN Offset ___ CI___ CT ____ Hit? __ PPO Byte: ____ Address Translation Example #3 Virtual 13 12 Address 0x0040 TLBT 11 10 9 8 7 TLBI 6 5 4 3 2 1 0 VPN VPN ___ VPO TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Physical Address CT CI 7 6 5 4 3 2 1 CO 0 11 10 9 8 PPN Offset ___ CI___ CT ____ Hit? __ PPO Byte: ____ ...
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This note was uploaded on 05/04/2010 for the course CS 333 taught by Professor Alarabi during the Spring '10 term at DeVry Cleveland D..

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