7-Inter_Memory-2

7-Inter_Memory-2 - 7-1Chapter 7 - MemoryPrinciples of...

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Unformatted text preview: 7-1Chapter 7 - MemoryPrinciples of Computer Architecture 2005Associative MappingA main memory block can load into any line of cacheMemory address is interpreted as tag and wordTag uniquely identifies block of memoryEvery lines tag is examined for a matchCache searching gets expensive- must simultaneously examine every lines tag for a match7-2Chapter 7 - MemoryPrinciples of Computer Architecture 2005Fully Associative Cache Organization7-3Chapter 7 - MemoryPrinciples of Computer Architecture 2005Tag 22 bitWord2 bitAssociative MappingAddress Structure Example24 bit address22 bit tag stored with each 32 bit block of dataCompare tag field with tag entry in cache to check for hitLeast significant 2 bits of address identify which byte is required from 32 bit data block7-4Chapter 7 - MemoryPrinciples of Computer Architecture 2005Associative Mapping SummaryAddress length = (s + w) bitsNumber of addressable units = 2s+wwords or bytesBlock size = line size = 2wwords or bytesNumber of blocks in main memory = 2s+ w/2w= 2sNumber of lines in cache = undeterminedSize of tag = s bits7-5Chapter 7 - MemoryPrinciples of Computer Architecture 2005Associate Mapping pros & consAdvantageFlexibleDisadvantagesCostComplex circuit for simultaneous comparison7-6Chapter 7 - MemoryPrinciples of Computer Architecture 2005Set Associative MappingCompromise between the previous twoCache is divided into vsets of klines eachm= vx k, where m: #linesi= jmod v, wherei: cache set numberj: memory block numberA given block maps to any line in a given setK-way set associate cache2-way and 4-way are common7-7Chapter 7 - MemoryPrinciples of Computer Architecture 2005Set Associative Mapping Examplem= 16 lines, v= 8 sets k = 2lines/set, 2 way set associative mappingAssume 32 blocks in memory, i= jmod vsetblocks...
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7-Inter_Memory-2 - 7-1Chapter 7 - MemoryPrinciples of...

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