{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

7-Inter_Memory-2 - 7-1 Chapter 7 Memory Associative Mapping...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon
7-1 Chapter 7 - Memory Principles of Computer Architecture © 2005 Associative Mapping A main memory block can load into any line of cache Memory address is interpreted as tag and word Tag uniquely identifies block of memory Every line’s tag is examined for a match Cache searching gets expensive - must simultaneously examine every line’s tag for a match
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
7-2 Chapter 7 - Memory Principles of Computer Architecture © 2005 Fully Associative Cache Organization
Background image of page 2
7-3 Chapter 7 - Memory Principles of Computer Architecture © 2005 Tag 22 bit Word 2 bit Associative Mapping Address Structure Example 24 bit address 22 bit tag stored with each 32 bit block of data Compare tag field with tag entry in cache to check for hit Least significant 2 bits of address identify which byte is required from 32 bit data block
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
7-4 Chapter 7 - Memory Principles of Computer Architecture © 2005 Associative Mapping Summary Address length = (s + w) bits Number of addressable units = 2 s+w words or bytes Block size = line size = 2 w words or bytes Number of blocks in main memory = 2 s+ w /2 w = 2 s Number of lines in cache = undetermined Size of tag = s bits
Background image of page 4
7-5 Chapter 7 - Memory Principles of Computer Architecture © 2005 Associate Mapping pros & cons Advantage Flexible Disadvantages Cost Complex circuit for simultaneous comparison
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
7-6 Chapter 7 - Memory Principles of Computer Architecture © 2005 Set Associative Mapping Compromise between the previous two Cache is divided into v sets of k lines each m = v x k , where m : #lines i = j mod v , where i : cache set number j : memory block number A given block maps to any line in a given set K-way set associate cache 2-way and 4-way are common
Background image of page 6
7-7 Chapter 7 - Memory Principles of Computer Architecture © 2005 Set Associative Mapping Example m = 16 lines, v = 8 sets k = 2
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 8
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}