Lect_04 - ECE 442 ECE 442 SolidState Devices & Circuits 4....

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CE 442 ECE 442 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine lectrical & Computer Engineering Electrical & Computer Engineering University of Illinois [email protected] ECE 442–Jose Schutt Aine 1
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Digital Circuits V IH : Input voltage at high state V IHmin V : Input voltage at low state V max IL ILmax V OH : Output voltage at high state V OHmin V OL : Output voltage at low state V OLmin Likewise for current we can define Currents into input I  I max I H  I Hmax Currents into output IH IHmax I IL  I ILmax OH OHmax I OL  I OLmax ECE 442–Jose Schutt Aine 2
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Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC In low state: noise margin is NM L In high state: noise margin is L IL OL NM V V  NM H NM L NM H H OH IH NM V V V IL and V IH are the points where the slope of the VTC=-1 An ideal VTC will maximize noise margins ECE 442–Jose Schutt Aine 3 /2  L HD D NM NM V Optimum:
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Switching Time & Propagation Delay input output ECE 442–Jose Schutt Aine 4
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Switching Time & Propagation Delay t r =rise time (from 10% to 90%) t f =fall time (from 90% to 10%) t pLH =low-to-high propagation delay high w propagation delay t pHL =high-to-low propagation delay Inverter propagation delay:   1 2 pp L H p H L tt t ECE 442–Jose Schutt Aine 5
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VTC and Noise Margins For a logic-circuit family employing a 3-V supply, suggest an ideal set of values for V th , V IL , V IH , V OH , NM L , NM H . Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply? 0 ; 00 V V V V Ideal 3V logic implies: 3. 0; 0 .0 OH DD OL VV  /2 3.0/2 1.5 ; th DD V /2 1.5 ; /2 1.5 IL DD IH DD V V V V ECE 442–Jose Schutt Aine 6
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VTC and Noise Margins 3.0 1.5 1.5 HO HI H NM V V V  1.5 0.0 1.5 LI L O L NM V V V Inverting transfer characteristics The gain in the transition region is: 30 00 / 15 15 V V V         /3 . 00 . 0/ 1 . 51 .5 OH OL IH IL VV  /0 / V  ECE 442–Jose Schutt Aine 7 3/0
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CMOS Noise Margins When inverter threshold is at V DD /2 , the noise margin NM H and NM L are equalized 32 83 H LD D t h NM NM V V      : noise margin for high input NM L : noise margin for low input oise margins are typically around 0 4 D close to half power- upply voltage V th : threshold voltage Noise margins are typically around 0.4 V DD ; close to half power supply voltage CMOS ideal from noise-immunity standpoint ECE 442–Jose Schutt Aine 8
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Switching Circuit ECE 442–Jose Schutt Aine 9
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Nonideal Switch 1 sc low sc L R VV R R 1 so high so L R R R ECE 442–Jose Schutt Aine 10
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IV Characteristics of Switches Ideal switch Non-ideal switch ECE 442–Jose Schutt Aine 11
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Complementary Switches 1 sc low sc so R VV R R 1 so high so sc R R R ECE 442–Jose Schutt Aine 12
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This note was uploaded on 05/05/2010 for the course ECE 329 taught by Professor Franke during the Spring '08 term at University of Illinois at Urbana–Champaign.

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Lect_04 - ECE 442 ECE 442 SolidState Devices & Circuits 4....

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