Lect_05 - CE 442 ECE 442 Solid State Devices &...

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Unformatted text preview: CE 442 ECE 442 Solid State Devices & Circuits 5. CMOS Logic Circuits Jose E. Schutt-Aine lectrical & Computer Engineering Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 442 Jose Schutt Aine 1 Digital Logic - Generalization De Morgans Law ... ... A B C A B C ... ... A B C A B C Distributive Law ) ( ) B AC BC BD A B C B C D General Procedure ( ) ( ) AB AC BC BD A B C B C D 1. Design PDN to satisfy logic function 2. Construct PUN to be complementary of PDN in every way 3. Optimize using distributive rule ECE 442 Jose Schutt Aine 2 CMOS Logic Gate Circuits Two Networks Pull-down network (PDN) with NMOS Pull-up network (PUN) with PMOS PUN conducts when inputs are low and consists of PMOS transistors PDN consists of NMOS transistors and is active when inputs are high PDN and PUN utilize devices In parallel to form OR functions In series to form AND functions ECE 442 Jose Schutt Aine se es to o u ct o s 3 Pull-Down Networks Y A B Y A B ECE 442 Jose Schutt Aine 4 Pull-Up Networks Y A B Y A B ECE 442 Jose Schutt Aine 5 asic...
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Lect_05 - CE 442 ECE 442 Solid State Devices &...

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