Question 2
(50 points)
It’s now May, you’ve passed the course and managed to land a job at a company that designs and builds
digital control systems.
They hand you a printed circuit board that was pulled out of a 20 year old system
and ask you to re-implement the circuit using current technology.
There is no question of replacing the
system - it has a 30 year lifetime, but the circuit board they handed you is completely fried (literally) and
has to be replaced.
Unfortunately there are absolutely no replacement parts or documentation available
(the manufacturer is out of business).
Your job - reverse engineer the circuit so that a new one may be
fabricated.
The board is implemented using 7400 transistor-transistor logic (TTL).
You manage to find a TTL data
book and determine that the circuit is comprised of J-K flip-flops and a variety of logic gates.
After
poring over the board for a day you trace out the circuit diagram shown below in Figure 2.1.
You are
now ready to reverse engineer the circuit.
a)
The first step is to determine the 6 flip-flop equations corresponding to J0, K0, J1, K1, J2, and K2
respectively.
This is accomplished by tracing through the schematic.
Next derive the next-state
equation corresponding to each flip-flop, and use these equations to fill in the state transition table
corresponding to the circuit.
Also produce the corresponding state diagram.
First Step:
Work out the equations for J0, K0, J1, K1, J2 and K2. By inspection, we can see that everything is done
with NAND-NAND logic, so every input is a sum of products.
We can then copy down the sum of
products form just by looking at the left-most inputs, as follows (working from top-to-bottom on the
diagram, and putting the inputs in the order M, Q2, Q1, Q0):
J2 =
M' Q1' Q0' + M Q1' Q0 + M' Q1 Q0
K2 =
Q1' Q0' + M' Q1'
J1 =
M Q2' Q0' + M Q2 Q0 + M' Q2' Q0
K1 =
M Q2' Q0' + M' Q2 Q0 + M Q2 Q0
Note that J0 has an input, Q1, to the second level NAND gate which is inverted.
This is the same as
putting Q1 through a NOT gate (i.e. a 1-input NAND gate) before putting it through the second level
NAND gate, so this means that one of the sum of products terms is:
Q1.
A similar thing happens with
Q2 and K0.
So, the equations are:
J0 =
M' Q2 + M Q2' + Q1
K0 =
M' Q1' + M Q1 + Q2
Next Step:
Derive and fill in the next-state equations for the J-K flip-flops.
Remember that for a J-K flip-flop,
Q
ˆ
= J
Q' + K' Q.
So, we can compute each of the
Q
ˆ
's as follows:
Flip-Flop 2:
Q
ˆ
2
= J2 Q2' + K2' Q2