HW4_S - 0306-250 Assembly Language Programming Fall 2009...

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Unformatted text preview: 0306-250 Assembly Language Programming Fall 2009 Homework Four Solution 1. Describe the details of initializing the SCI and ECT (timer) to generate interrupt requests. Be sure to describe all bits of the control registers that must be set and/or cleared and why each bit/field must have the value that you indicate. SCI: To initialize the SCI to generate interrupts as used in lab for serial I/O, bits 5 (RIE) and 7 (TIE) in SCI Control Register 2 (SCICR2) must be set. Setting bit 7 (i.e., making it 1) enables transmit interrupts, and setting bit 5 enables receive interrupts. Receive interrupts occur when a character has been received, which is when the RDRF flag is set. Transmit interrupts occur when the SCI is ready to transmit a character, which is when the TDRE is set. (Note there are two other types of SCI interrupts not used in lab.) ECT: To initialize the ECT to generate interrupts as used in lab for timer output compare, it is necessary both to initialize the ECT Timer Input Capture/Output Compare Register (TIOS) with a 1 in bit 7 (IOS7) to set channel 7 for output compare and also to set bit 7 (C7I) in ECT Timer Interrupt Enable Register (TIE) to enable channel 7 output compare interrupts. The IOS7 bit (7) in TIOS indirectly control the interrupt in the sense that the bit indicates the circumstances when an interrupt should be generated, but TIE bit 6 (C7I) explicitly enables/disables the IRQ. 2. List the differences between (1) a subroutine and (2) an interrupt handler. · · · · Their invoking sources are different: subroutines are executed as a result of being called explicitly from program code, (e.g., BSR or JSR); interrupt handlers (ISRs) are executed in response to externally generated IRQs. Subroutines must have matched call and return code in the program—(i.e., each BSR/JSR must be followed by RTS in the subroutine). Interrupt handlers use RTI without any matched explicit invocation from the CPU. Before the CPU begins executing the code of a subroutine, the CPU saves PC (the address of the instruction following the BSR) to the system stack. Before executing an interrupt handler, the CPU will check CCR’s I bit to make sure it is cleared (i.e., interrupts are not masked); if so, the CPU will then save PC (the address of the next instruction), X, Y, B, A, and CCR to the system stack. For a subroutine, it is known exactly where and when the subroutine should be executed (since the program includes the calling code); however, it can not be known (i.e., predicted) when an interrupt handler will be executed or where the program will be executing when it occurs. Page 1 of 2 0306-250 20091 Homework Four Solution Page 2 of 2 3. Explain what happens from the time an IRQ is asserted until the time the RTI instruction is executed. (Note: There are many steps involved, so take your time and be specific.) HCS12 Exception Processing: 1. Hardware device asserts interrupt signal. 2. If the I bit of CCR is cleared, HCS12 decodes source of interrupt to determine vector table entry. 3. The current values of PC (return address), X, Y, B, A, and CCR are pushed onto the stack as the address at the vector table entry is loaded into the program counter. 4. The I bit of the CCR is set to mask subsequent interrupts. 5. Execution begins at the address specified in the vector table entry for the interrupt service routine (ISR). 6. The ISR terminates by executing the RTI instruction, which pops CCR, A, B, Y, X, and PC values from the stack, and program execution resumes at the point where the program was interrupted. 4. Explain the differences among (1) interrupts, (2) exceptions, and (3) traps. · · · Interrupts are generated by hardware, which is external to the CPU, and are a result of the normal operation of hardware devices. Exceptions are generated implicitly by software executing on the CPU and are a result of “exceptional” or erroneous situations. Although these events are initiated by software, they are not part of the designed control flow of the program. Traps are generated explicitly by software execution on the CPU and are a direct result of software that is part of (and critical to) the designed control flow of the program. Grading Criteria · · · · · · 10 points: Overall presentation—accurate and thorough answer/solution, which gives the answer and explains how it was derived 20 points: Question 1 20 points: Question 2 30 points: Question 3 20 Points: Question 4 ...
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This note was uploaded on 05/06/2010 for the course EECC 0306-250 taught by Professor Roymelton during the Fall '10 term at RIT.

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