lecture06 - 0306-250 Assembly Language Programming Lecture...

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Unformatted text preview: 0306-250 Assembly Language Programming Lecture Six: • Loop Constructs • Operands WHILE Statement Control Flow Graph while (Predicate) { Loop Body } Predicate ? T Loop Body F WHILE Predicate ? Branch ¬ Predicate Loop Body Branch WHILE LABEL 2 WHILE Statement Example HCS12 while (Predicate) { Loop Body } ; X: B ; Y: A ; VarA: memory VarA While: ldab ble VarA EndWhile LoopBody: aba decb X = VarA; while (X>0) { Y += X; X--; } bra While EndWhile: 3 DO Statement Control Flow Graph do { Loop Body } while (Predicate); DO Loop Body Loop Body Predicate ? T F Predicate ? Branch Predicate 4 DO Statement Example HCS12 do { Loop Body } while (Predicate); ; X: ; Y: ; A: B A memory VarA ldab Do: X = VarA; do { Y += X; X--; } while (X>0); VarA aba decb bgt Do EndDo: 5 FOR Statement Control Flow Graph for (Init; Test; Step) { Loop Body } FOR Init. Init. Test ? Test ? T F Branch ¬ Predicate Loop Body Loop Body Step Step Branch Test? LABEL 6 FOR Statement Example HCS12 for (Init; Test; Step) { Loop Body } ; X: B ; Y: A ; VarA: memory VarA ldab VarA ForTest: ble EndFor ForLoop: for (X=A; X>0;X--) { Y += X; } ForInit: aba ForStep: decb bra ForTest EndFor: 7 Addressing Modes (HCS12) • Each mode allows a different type of operand (M) – – – – – – – – – – – – – • Immediate Register Direct (Inherent) Memory Direct (Direct; Extended) Register Indirect (Indexed) Register Indirect with Displacement (Indexed) Register Indirect with Index (Indexed) Register Indirect Post-decrement (Indexed) Register Indirect Post-increment (Indexed) Register Indirect Pre-decrement (Indexed) Register Indirect Pre-increment (Indexed) Memory Indirect from Register Indirect with Displacement (Indexed Indirect) Memory Indirect from Register Indirect with Index (Indexed Indirect) Relative (branch instructions are PC-relative) Each instruction may allow different addressing modes 8 Immediate Addressing • Operand: #opr8 or #opr16 – Specified as part of instruction • Value coded into machine instruction • No memory access other than instruction – Constant – Only valid for data source • Immediate source operand examples ldaa addd ora Cpd #25 #$C036 #%0010000 #16384 9 Register Direct Addressing (Inherent) • Operand: abcdxys – Contents of register • Register encoded into machine instruction aba sba asla exg D a,b – More flexible than immediate • Variable content • Fixed location CPU X Y SP Registers – Data: R[abcdxys] 10 Memory Direct Addressing • Operand: opr8 (direct) or opr16 (extended) – Specified by actual address • Encoded into machine instruction • Numeric¾address lda ldd 102 NumB 104 NumC 106 NumD 108 NumE $10 $2200 10A NumF • Symbolic¾label EQU $100 addd X std NumD MyData: SECTION NumD: DS.W 1 100 NumA Memory X: ;Here MyData maps to $100 – Data: M[opr8] or M[opr16] 11 Register Indirect Addressing (Indexed) 100 NumA • Operand: (xysp) 102 NumB – Specified by address in register – More flexible than absolute 104 NumC 106 NumD 108 NumE • Variable content residing at • Variable address 10A NumF Memory – Example ldx ldy ldd addd #$104 #NumF ,x ,y X ;NumC ;NumF – Data: M[R[xysp]] CPU Y SP PC Index Registers 12 Register Indirect with Displacement Addressing (Indexed) • Operand: (opr5,xysp), (opr9,xysp), or (opr16,xysp) 100 NumA 102 NumB – Specified by two components 104 NumC 106 NumD • Base address in index register • Signed displacement (i.e., constant offset) 108 NumE 10A NumF – More flexible than register indirect • Variable content residing at • Variable address with offset -4 #$108 -4,x 2,x ; &NumE ; D ß NumC ; D ß D + NumF – Data: M[R[xysp]+opr] + X CPU – Example ldx ldd addd Memory Y SP PC Index Registers 13 ...
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This note was uploaded on 05/06/2010 for the course EECC 0306-250 taught by Professor Roymelton during the Fall '10 term at RIT.

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