Lecture09 - 0306-250 Assembly Language Programming Lecture...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 0306-250 Assembly Language Programming Lecture Nine: Device Programming • Freescale Microcontroller Project Board (PBMCUSLK) • Serial I/O fundamentals • HSC12 Asynchronous Serial Communications Interface (SCI) Device Programming Make use of a peripheral device • Chip • Subsystem • Low-level programming for device (typically assembly language) – – – – Initialize Control Change Use 2 Device I/O Characteristics • Very slow At least an order of magnitude slower than CPU • Not continuous – Sporadic – Periodic • No need for undivided attention of CPU • Device-specific format (programming) 3 HCS12 Device I/O Characteristics Memory-mapped I/O • I/O device has “memory” location (addresses) • Memory location hardware dependent – HW system design determines address – Same device can be at a different address on a different processor or system • Peripheral devices do not need special instructions Already have instructions to copy data to and from a memory address 4 Freescale Microcontroller Project Board Project Board Factsheet (BRMCSTDNTLEARN_FS) 5 Serial I/O Fundamentals Lecture Nine: Device Programming • Freescale Microcontroller Project Board (PBMCUSLK) FSerial I/O fundamentals • HSC12 Asynchronous Serial Communications Interface (SCI) PC Terminal and Project Board Connection Project Board Terminal Dedicated System (HW and SW) Asynchronous Serial Communications Interface SCI Serial Interface Line Drivers Serial Cable System SW Device Driver SW Serial Interface Line Drivers Asynchronous Transmission 7 HCS12 SCI Data Stream • Divided into individual bits • Character-oriented— groups of bits yield characters • Character: 7-8 information bits • Idle – Mark level (stop): High – Space level (start): Low (i.e., Mark¢) • Bit duration: T Determined by baud rate 8 Serial Character Transmission t T MARK SPACE START BIT Idle 1 0 1 0 1 0 1 0 STOP BIT One Character • One character—standard bit format – Start bit (1) – Data bits (7 or 8) —HCS12 SCI allows 7, 8, or 9 – Parity bit (None, Even, or Odd) – Stop bit(s) (1 or 2)—HCS12 SCI allows only one • 12 possible standard formats—7 common 9 Example Transmission: “DOG” DC.B 44,4F,47 ;'DOG' • 8N1: 8 data bits + no parity + 1 stop bit • 7E2: 7 data bits + even parity + 2 stop bits • 8O2: 8 data bits + odd parity + 2 stop bits Receiver • • • • Looks for start bit Waits until end of start bit Samples each successive bits at its center At end of character, compares parity bit to detect transmission error 10 Serial Interface Signals Serial Protocol RS-232 (recommended standard #232) • • • • • TxD: transmit data RxD: receive data RTS: request to send CTS: clear to send DCD: data carrier detect Transmitter Receiver TxD RxD RTS¢ DCD¢ CTS¢ Flow control • HW: RTS and CTS • SW: XON (^Q) and XOFF(^S) 11 HCS12 Asynchronous Serial Communication Interface (SCI) Lecture Nine: Device Programming • Freescale Microcontroller Project Board (PBMCUSLK) • Serial I/O fundamentals FHSC12 Asynchronous Serial Communications Interface (SCI) HCS12 SCI Asynchronous Serial Communications Interface (SCI) • Data formatting and control for serial communication • Data sheet link on course resources web page 13 HCS12 Block Diagram SCI MC9S12C Family Reference Manual, p. 20 14 SCI Block Diagram Serial Communications Interface (S12SCIV2) Block Description, p. 3. 15 • • • • SCI Registers Baud rate control registers (SCIBDH, SCIBDL) Control registers (SCICR1 , SCICR2) Status registers (SCISR1 , SCISR2 Data registers (SCIDRH, SCIDRL) – Read: Receive data register – Write: Transmit data register Serial Communications Interface (S12SCIV2) Block Description, p. 4. Two separate registers, which map to the same address 16 SCI Baud Rate Control Registers SCIBDH SCIBDL 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 • 13-bit divider of HCS12 bus clock Bus Clock SCIBR[12 : 0] = 16 ´ SCI Baud Rate • For lab, want 9600 baud – Bus clock: one-half external oscillator frequency – HSC12 module on project board has 4-MHz oscillator ê 0.5 ´ 4 ´ 106 ú SCIBR[12 : 0] = ê ú = 13 ë 16 ´ 9600 û 17 SCI Control Register 1 7 6 LOOPS 5 4 3 2 1 0 SCIWAI RSRC M WAKE ILT PE PT Operation mode — Want one start bit, eight data bits, and one stop bit? M : Mode: 1 start bit, 8¢/9 data bits, 1 stop bit: 0 — Want no parity? PE : Parity enable: 0 PT : Parity type even¢/odd : X — Want normal operation? LOOPS : Loop operation enable: 0 RSRC : Receiver source internal¢/external: X — Want enabled in wait mode? SCIWAI : SCI stop in wait mode: 0 — Want idle line wake-up? WAKE : Idle¢/address line wake-up: 0 — Want idle character bit count to start after start bit? ILT : Idle line type: after start¢/stop: 0 18 7 TIE SCI Control Register 2 6 5 4 3 2 1 0 TCIE RIE ILIE TE RE RWU SBK • Transmitter control — Want enabled? TE : Transmitter enable: 1 — Want no break characters sent? SBK : Send break characters: 0 — Want interrupts disabled? TIE : Transmitter interrupt enable: 0 TCIE : Transmission complete interrupt enable: 0 • Receiver control — Want enabled? RE : Receiver enable: 1 — Want normal operation (not wake-up)? RWU : Receiver wake-up: 0 — Want interrupts disabled? RIE : Receiver full interrupt enable: 0 ILIE : Idle line interrupt enable: 0 19 SCI Status Register 1 (read only) TDRE TC RDRF IDLE OR NF FE PF 7 6 5 4 3 2 1 0 • RDRF: Receive data register (RDR) full – 1: new data received; receive SCIDR ready to be read – 0: no new data received; receive SCIDR not ready to be read • TDRE: Transmit data register (TDR) empty – 1: no data to transmit; transmit SCIDR ready for next character – 0: still transmitting current transmit SCIDR contents; not ready for more data to transmit 20 ...
View Full Document

Ask a homework question - tutors are online