lecture10 - 0306-250 Assembly Language Programming Lecture...

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Unformatted text preview: 0306-250 Assembly Language Programming Lecture Ten: SCI Polled Transmit •SCI Initialization •Polled Transmit Algorithm •PutChar Subroutine HCS12 Memory Map MC9S12C Family Reference Manual, p. 21 2 • • • • SCI Registers Baud rate control registers (SCIBDH, SCIBDL) Control registers (SCICR1 , SCICR2) Status registers (SCISR1 , SCISR2 Data registers (SCIDRH, SCIDRL) – Read: Receive data register – Write: Transmit data register Serial Communications Interface (S12SCIV2) Block Description, p. 4. Two separate registers, which map to the same address 3 Include File EQUates for SCI Registers INCLUDE 'mc9s12dt256b.inc‘ ; NOTE: SCI0 base address is $00C8 ;*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 *** SCI0BDH: equ $000000C8 ; SCI0Base + $0000 ;*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 *** SCI0BDL: equ $000000C9 ; SCI0Base + $0001 ;*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA *** SCI0CR1: equ $000000CA ; SCI0Base + $0002 ;*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB *** SCI0CR2: equ $000000CB ; SCI0Base + $0003 ;*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC *** SCI0SR1: equ $000000CC ; SCI0Base + $0004 ;*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD *** SCI0SR2: equ $000000CD ; SCI0Base + $0005 ;*** SCI0DRH - SCI 0 Data Register High; 0x000000CE *** SCI0DRH: equ $000000CE ; SCI0Base + $0006 ;*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF *** SCI0DRL: equ $000000CF ; SCI0Base + $0007 4 SCI0 Initialization • Set SCI0 baud rate SCI0BDH, SCI0BDL • Set SCI0 operation/format SCI0CR1 • Set SCI0 operation/enable SCI0CR2 5 Include File EQUates for SCI CR2 INCLUDE 'mc9s12dt256b.inc‘ ;*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB *** SCI0CR2: equ $000000CB ; bit numbers SCI0CR2_SBK: SCI0CR2_RWU: SCI0CR2_RE: SCI0CR2_TE: SCI0CR2_ILIE: SCI0CR2_RIE: SCI0CR2_TCIE: SCI0CR2_SCTIE: equ equ equ equ equ equ equ equ ; bit position masks mSCI0CR2_SBK: equ mSCI0CR2_RWU: equ mSCI0CR2_RE: equ mSCI0CR2_TE: equ mSCI0CR2_ILIE: equ mSCI0CR2_RIE: equ mSCI0CR2_TCIE: equ mSCI0CR2_SCTIE: equ 0 1 2 3 4 5 6 7 ; ; ; ; ; ; ; ; Send Break Bit Receiver Wakeup Bit Receiver Enable Bit Transmitter Enable Bit Idle Line Int. En. Bit Receiver Full Int. Enable Bit Transmission Complete Int. En. Bit Transmitter Int. En. Bit %00000001 %00000010 %00000100 %00001000 %00010000 %00100000 %01000000 %10000000 6 Polled Transmit What does it mean? • Poll – Question or canvas – Test • Transmit Send HCS12 SCI application • Poll TDRE bit of SCI’s status register 1 until SCI is ready to transmit TDRE = 1 • Write data to be transmitted, to TDR www.m-w.com 7 Polled Transmit Algorithm • Algorithm repeat { check TDRE bit of SCI SR } until (TDRE = 1) put character to transmit into SCI TDR • Note: to clear TDRE condition 1.Read SCI SR containing TDRE 2.Write to SCI TDR (must occur in this order) 8 Include File EQUates for SCI SR1 INCLUDE 'mc9s12dt256b.inc‘ ;*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC *** SCI0SR1: equ $000000CC ; bit numbers SCI0SR1_PF: SCI0SR1_FE: SCI0SR1_NF: SCI0SR1_OR: SCI0SR1_IDLE: SCI0SR1_RDRF: SCI0SR1_TC: SCI0SR1_TDRE: equ equ equ equ equ equ equ equ ; bit position masks mSCI0SR1_PF: equ mSCI0SR1_FE: equ mSCI0SR1_NF: equ mSCI0SR1_OR: equ mSCI0SR1_IDLE: equ mSCI0SR1_RDRF: equ mSCI0SR1_TC: equ mSCI0SR1_TDRE: equ 0 1 2 3 4 5 6 7 ; ; ; ; ; ; ; ; Parity Error Flag Framing Error Flag Noise Flag Overrun Flag Idle Line Flag Receive Data Register Full Flag Transmit Complete Flag Transmit Data Register Empty Flag %00000001 %00000010 %00000100 %00001000 %00010000 %00100000 %01000000 %10000000 9 Checking a Specific Bit within a Byte • mSCI0SR1_TDRE is %10000000 – 1 in TDRE bit position of SCI0SR1 – 0 in all other bit positions • Strategy that generally does not work ü ; Set Z if TDRE=1 ü ldaa SCI0SR1 û cmpa #mSCI0SR1_TDRE • ; Works only if no other SCI0SR1 bits set • Strategy that always works ü ; Set Z if TDRE=0 ü ldaa SCI0SR1 ü anda #mSCI0SR1_TDRE 10 ...
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