Lecture20 - 0306-250 Assembly Language Programming Lecture...

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Unformatted text preview: 0306-250 Assembly Language Programming Lecture Twenty: Analog to Digital (A/D) Conversion (Chapter 17) •HSC12 Analog-to-Digital Converter (ATD) •Registers •Algorithm HCS12 A/D Converter Analog-to-digital converter (ATD, ADC, or A/D) • Converts real-world analog signal to digital representation • Data sheet link on course resources web page 2 HCS12 Block Diagram A/D MC9S12C Family Reference Manual, p. 20 3 ATD Block Diagram ATD_10B8C Block User Guide V02.12 (S12ATC10B8CV2), p. 10. 4 ATD Registers ATD_10B8C Block User Guide V02.12 (S12ATC10B8CV2), p. 13. 5 ATD Control Register 2: A/D Power Up 7 6 5 4 3 2 1 0 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF Power up — Want A/D function? ADPU : Normal A/D function: 1 — Want default operation? All other bits: 0 Must wait 20 ms after power up to use. — Other “useful” program code — Dedicated time delay code movb #mATD0CTL2_ADPU,ATD0CTL2 Suggestion: third instruction of program— 1) Initialize SP, 2) Disable interrupts, 3) Power up A/D 6 ATD Control Register 3: A/D Conversion Sequence 7 6 5 4 3 2 1 0 0 S8C S4C S2C S1C FIFO FRZ1 FRZ2 Conversion sequence length — Want default 1 channel conversion per sequence? S8C:S4C:S2C:S1C : 4: 0000 — Want default operation? All other bits: 0 movb #mATD0CTL3_S1C,ATD0CTL3 7 ATD Control Register 4: A/D Resolution, Sampling Time, and Clock Selection 7 6 5 4 3 2 1 0 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Resolution — Want 10-bit resolution? SRES8 : 10¢/8 bits: 0 Sample time select — Want 4-clock sample time? SMP1:SMP0 : 2SMP1:SMP0 + 1 clocks: 01 Clock prescaler (bus clock divisor) — Want minimum divisor? PRS4:PRS0 : 2(PRS4:PRS0 + 1): 00000 movb #mATD0CTL4_SMP0,ATD0CTL4 8 ATD Control Register 5: A/D Input Multiplexer and Input Scanner (Part 1) 7 6 5 4 3 2 1 0 DJM DSGN SCAN MULT 0 CC CB CA Result register data justification — Want right-justified data? DJM : Left¢/Right: 1 Result register data signed — Want unsigned? DSGN : Signed: 0 Conversion sequence mode — Want single sequence? SCAN : Single¢/Continuous: 0 9 ATD Control Register 5: A/D Input Multiplexer and Input Scanner (Part 2) 7 6 5 4 3 2 1 0 DJM DSGN SCAN MULT 0 CC CB CA Multichannel sample mode — Want to sample one channel? MULT : One¢/Multiple: 0 Analog input channel select code — Want channel 3? CC:CB:CA : (First) channel number: 011 movb #(mATD0CTL5_DJM|mATD0CTL5_CB|mATD0CTL5_CA),ATD0CTL5 10 ATD Status Register 0 7 6 5 4 3 2 1 0 SCF 0 ETORF FIFOR 0 CC2 CC1 CC0 Sequence complete flag: SCF — 0 : Conversion sequence not complete — 1 : Conversion sequence completed Poll on SCF to know when to read data PollATD: brclr ATD0STAT0,#mATD0STAT0_SCF,PollATD 11 ATD Result Registers Eight 16-bit result registers — ATD0DRnH : High byte of result register n — ATD0DRnL : Low byte of result register n Left-justified result data 12 A/D Algorithm • Initialization (once in program) – Write ATD0CTL2 – Write ATD0CTL3 – Write ATD0CTL4 • Start conversion – Write ATD0CTL5 • Get results – Poll on SCF in ATD0STAT0 – Read digital conversions in result register • Read ATD0DR0 13 ...
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This note was uploaded on 05/06/2010 for the course EECC 0306-250 taught by Professor Roymelton during the Fall '10 term at RIT.

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