Lecture25 - 0306-250 Assembly Language Programming Lecture Twenty-Five Exception Processing(Text Chapter 12 •Interrupts •Exceptions •ISR

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Unformatted text preview: 0306-250 Assembly Language Programming Lecture Twenty-Five: Exception Processing (Text Chapter 12) •Interrupts •Exceptions •ISR Processing •Traps HCS12 Interrupt Vector Table • Associates an ISR with an IRQ • Memory addresses reserved for interrupt vector table: $FF80–$FFFF – 128 ($80) bytes à 64 entries of 2 bytes each – Each entry: word address of ISR associated with IRQ Note: HCS12 CPU can handle up to 128 interrupt vectors but number implemented varies by specific HCS12 derivative (e.g., numbers above are for Freescale 9S12DT256) 2 Generic CPU IRQ Vector Schemes CPU designs for IRQ using vectors • Vectored interrupts: Interrupting device provides vector at time of interrupt • Autovector interrupts: Interrupting device does not provide a vector number 3 Vectored Interrupts Interrupting device provides vector at time of interrupt •Vector: interrupt vector table entry number •Flexible: SW designer has ability to control vectors used by each device •Multiple devices can share same IRQ but have different ISRs 4 Autovector Interrupts Interrupting device does not provide vector •Autovector: predefined vector table entry based on IRQ number •Fixed: each IRQ maps to exactly one ISR •Simpler to implement in hardware 5 HCS12 Interrupt Vector Table and IRQ Priority HCS12 references have tables of IRQs • MC9S12DT256 Device User Guide, Table 5-1, pp. 75-76 • Text (Cady), Table 12-1 • Specifies each IRQ – Vector (location of pointer to ISR) – Source (device generating IRQ) – Mask (CPU mechanism to ignore IRQ) – Enable (device ability to generate IRQ) 6 HCS12 Interrupt Vector Table (Partial) MC9S12DT256 Device User Guide, v. 03.07, p. 75 7 Exceptions • Allow software to interrupt program flow • Effects similar to interrupts – Program resumes at point of interruption – No disruption of program instructions or data • Occur in response to different source – Interrupt: in response to HW event – Exception: in response to SW event 8 Common CPU Exceptions—not HCS12 • Divide by zero Exception raised because results meaningless • Privilege violation Exception raised if program in user mode attempts to execute instruction restricted to supervisor mode • Trace Exception used by debuggers to allow single-stepping program execution • Trap on overflow Exception raised when the overflow bit is set 9 ISR Processing • Must execute invisibly to the interrupted program – Return address saved on stack before ISR executed – All CPU registers saved on stack before ISR executed X, Y, A, B, and CCR • Must clear whatever caused IRQ • Must use RTI to return from ISR (not RTS) – Restores all CPU registers from stack – Restores PC from stack 10 Traps • Software interrupts (SWIs): SWI #n, where n Î [0, 255] • Cause execution of ISR specified at $FFF6 • Program execution continues immediately following SWI instruction • Non-maskable and 5th highest priority 11 Trap Use • Basic block of functionality: subroutine • Subroutines can be called only within program • Mechanism to call subroutine of another program (e.g., operating system) – HCS12 allows 256 traps (SWI) – No standard trap operation across systems – OS specification determines trap characteristics 12 General Trap Characteristics • Parameters: passed through registers • Different from all other ISRs – Execution not transparent to program – Execution is part of program: ~subroutine • Perform functions specific to device or OS – – – – Example: get keyboard input Example: display character on screen Different for each system: depends on HW design Can allow program to work on multiple systems, independent of HW design 13 Common Trap Functions/Handling • Most common functions – Input/output (I/O) – Device drivers • Programs do not install trap handler – Traps invoked to perform services – Exception: programs that provide services • Device drivers • Custom library 14 ...
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This note was uploaded on 05/06/2010 for the course EECC 0306-250 taught by Professor Roymelton during the Fall '10 term at RIT.

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