S12SCIV2 - Chapter 1 Serial Communications Interface...

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Freescale Semiconductor 1 Chapter 1 Serial Communications Interface (S12SCIV2) Block Description 1.1 Introduction This block guide provide an overview of serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 1.1.1 Glossary IRQ — Interrupt Request LSB — Least Significant Bit MSB — Most Significant Bit NRZ — Non-Return-to-Zero RZI — Return-to-Zero-Inverted RXD — Receive Pin SCI — Serial Communication Interface TXD — Transmit Pin 1.1.2 Features The SCI includes these distinctive features: Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format 13-bit baud rate selection Programmable 8-bit or 9-bit data format Separately enabled transmitter and receiver Programmable transmitter output parity Two receiver wake up methods: — Idle line wake-up — Address mark wake-up Interrupt-driven operation with eight flags: — Transmitter empty
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Serial Communications Interface (S12SCIV2) Block Description 2 Freescale Semiconductor — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection 1.1.3 Modes of Operation The SCI operation is the same independent of device resource mapping and bus interface mode. Different power modes are available to facilitate power saving. 1.1.3.1 Run Mode Normal mode of operation. 1.1.3.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI. 1.1.3.3 Stop Mode The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI.
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Serial Communications Interface (S12SCIV2) Block Description Freescale Semiconductor 3 1.1.4 Block Diagram Figure 1-1 is a high level block diagram of the SCI module, showing the interaction of various functional blocks.
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This note was uploaded on 05/06/2010 for the course EECC 0306-250 taught by Professor Roymelton during the Fall '10 term at RIT.

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S12SCIV2 - Chapter 1 Serial Communications Interface...

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