EECC351_homework1_20092

EECC351_homework1_20092 - is ‘1’ only when there is an...

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EECC 351 HW #1 Due Wednesday 1/13/2010. Show your steps clearly and cleanly . 1. (40 pts) Construct and test (simulate) two VHDL models of a 16bit adder. The first model will use for loop and the second model will use while loop. 2. (40 pts) Construct and test (simulate) two VHDL models of an 8bit parity detector - the output of the detector
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Unformatted text preview: is ‘1’ only when there is an even number of ‘1’ on all 8 inputs. The first model will use for loop and the second model will use while loop. 3. (20 pts) Construct and simulate structural model of a 4 bit adder that uses 1 bit full adders as components....
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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