EECC351_homework2_20092 - start signal, computes the first...

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EECC 351 HW #2 Due Friday 1/20/2010. Show your steps clearly and cleanly . 1. (50 pts) Construct and test VHDL model of a negative-edge-triggered JK flip-flop. 2. (50 pts) The Fibonnacci series is the following series of numbers 0, 1, 1, 2, 3, 5, 8, 13, 21, etc. This sequence can be defined as follows: F0 = 0 F1 = 1 Fi = F(i-1) + F(i-2) i>1; Except the first two numbers of the series, the i-th member of the series is the sum of the (i-1) and (i-2) members of the series. Assume that the device you model is activated with the
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Unformatted text preview: start signal, computes the first 20 numbers of the series ( F0 through F19 ), and sends the first Fibonnacci number to the output 60 ns later. After that all the other numbers are sent to the output in serial every 5 ns. The entity of the model should have the following ports: start : in std_logic; Fibonnacci : out integer; You have to use loop, wait until and wait for statements in your architecture. Use array of integers structure to store the numbers. Simulate it to verify the correctness of the model....
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This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

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