Unformatted text preview: start signal, computes the first 20 numbers of the series ( F0 through F19 ), and sends the first Fibonnacci number to the output 60 ns later. After that all the other numbers are sent to the output in serial every 5 ns. The entity of the model should have the following ports: start : in std_logic; Fibonnacci : out integer; You have to use loop, wait until and wait for statements in your architecture. Use array of integers structure to store the numbers. Simulate it to verify the correctness of the model....
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- Winter '10
- Addition, Summation, Natural number, negative-edge-triggered JK flip-flop