This preview shows page 1. Sign up to view the full content.
Unformatted text preview: same as presented in the picture below. Simulate the model to verify its correctness for n=4. Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D En En En En Mux2 Mux2 Mux2 Mux2 ... ... D(0) D(1) D(2) D(n-1) Q(0) Q(1) Q(2) Q(n-1) clk clear en mode serial_in serial_out...
View Full Document
This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.
- Winter '10