HDL_lab0 - tools No formal report is required for this...

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EECC 0306- 351: Hardware Description Language Lab LAB#0 The objectives of this lab exercise are: 1) To learn how to write a simple VHDL source code, compile it and simulate using the ModelSim’s tools. 1) Follow the instructions from ModelSim-Tutorial.pdf and example given by instructor to practice using ModelSim’s
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Unformatted text preview: tools No formal report is required for this introductory lab – however you need to annotate your simulation results, draw simulated circuit, write its truth table and submit everything to your lab instructor/TA....
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