HDL_lab0 - tools No formal report is required for this...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
EECC 0306- 351: Hardware Description Language Lab LAB#0 The objectives of this lab exercise are: 1) To learn how to write a simple VHDL source code, compile it and simulate using the ModelSim’s tools. 1) Follow the instructions from ModelSim-Tutorial.pdf and example given by instructor to practice using ModelSim’s
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: tools No formal report is required for this introductory lab however you need to annotate your simulation results, draw simulated circuit, write its truth table and submit everything to your lab instructor/TA....
View Full Document

This note was uploaded on 05/06/2010 for the course EECC 0306-351 taught by Professor Marcinlukowiak during the Winter '10 term at RIT.

Ask a homework question - tutors are online